Sdram WR Retire Rate, Dram Opt RAS Precharge

SDRAM WR Retire Rate

The system designer must select the correct timing for data transfers from the write buffer to memory, according to DRAM specifications

The choice: 0WS, 1WS.

DRAM Opt RAS Precharge

The precharge time is the number of cycles it takes for the RAS to accumulate its charge before DRAM refreshes. If insufficient time is allowed, refresh may be incomplete and the DRAM may fail to retain data. The choice: Enabled, Disabled.

PCI Peer Concurrency

Peer concurrency means that more than one PCI device can be active at a time. The choice: Enabled, Disabled.

RAS Precharge Time

The Choice: 2T, 3T, 4T, 5T.

RAS to CAS Delay

TWhen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe).

The choice: 2T, 3T, 4T, 5T.

ISA Bus Clock Frequency

You can set the speed of the AT bus at one-third or one-fourth of the CPU clock speed. The choice: 7.159MHz, PCICLK/3, PCICLK/4.

Starting Point of Paging

This value controls the start timing of memory paging operations.

The choice: 1T, 2T, 4T, 8T.

NA# Enable

Selecting Enabled permits pipelining, in which the chipset signals the CPU for a new memory address before all data transfers for the current cycle are complete, resulting in faster performance. The choice: Enabled, Disabled.

L2 Cache Burst RD Cycle

These timing numbers are the pattern of cycles the CPU uses to read data from the cache. The choice: Normal, Delay 1T.

Asyn/Sync Mode CPU/DRAM

This feature can only be enabled when the frequency of CPU clock and the frequency of DRAM clock are the same and the skew between these two clocks should be zero. The choice: Asynchronous, Synchronous.

SDRAM CAS Latency

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer. The choice: 2T, 3T.