Intel Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion, 249323-003 Mdio Routing Port

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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion

Table 5. PHY Address Configuration Settings (Switch S1)

Jumper / Label

Description

 

 

S1-1 / ADD_0

Address <4:0> - Sets base address. Each port adds its port number (starting with 0)

 

to this address to determine its PHY address.

S1-2 / ADD_1

Switch “0” sets address bit to 0.

 

S1-3 / ADD_2

Switch “1” sets address bit to 10.

 

Note: To make all ports accessible within the 0 - 31 PHY address range, DO NOT

S1-4 / ADD_3

select a base address higher than 24.

 

 

Port 0 = Base + 0

 

Port 1 = Base + 1

 

Port 2 = Base + 2

S1-5 / ADD_4

Port 3 = Base + 3

Port 4 = Base + 4

 

 

Port 5 = Base + 5

 

Port 6 = Base + 6

 

Port 7 = Base + 7

 

 

4.3Alternate MDIO Routing Configuration

The MDIO and MDC signals may be routed either through the 40-pin connector for MII Port 0 (the standard configuration) or through an RJ-11 connector (J2), as shown in Table 6. In either configuration, the MII registers can be accessed for each port by setting the correct PHY address. Refer to the LXT9785/9785E Data Sheet for specific register definitions and functions. The standard configuration is to route MDIO through the Port 0 MII connector to the SmartBits Test Box by setting the pins for JP1 and JP2 to 2 & 3.

Note: MDIO sectionalization is not supported on this demo board.

Table 6. MDIO Routing (Port 0)

Desired Configuration

Jumper

Setting

Description

 

 

 

 

 

JP2

Jumper

Routes MDC0 through Port 0 MII Connector.

 

Pins 2 & 3

Route MDIO0 and MDC0

 

 

 

 

 

through MII

JP1

Jumper

Routes MDIO0 through Port 0 MII Connector.

 

Pins 2 & 3

 

 

 

 

 

 

 

 

JP2

Jumper

Routes MDC0 through RJ-11 Connector J2.

 

Pins 1 & 2

Route MDIO0 and MDC0

 

 

 

 

 

through RJ-11

JP1

Jumper

Routes MDIO0 through RJ-11 Connector J2.

 

 

Pins 1 & 2

 

 

 

 

 

 

 

Development Kit Manual

15

Document #: 249323

Revision #: 003

Rev. Date: January 24, 2002

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Contents January Development Kit ManualDocument # Revision # Rev. Date January 24 Contents Tables Date Revision Description Revision HistoryPage General Description FeaturesLXD9785 Pqfp MII Demo Board Equipment Requirements Fiber Register ConfigurationIntroduction OverviewTypical Test Setup Typical SetupLXD9785/9785E SS-SMII Fiber Demo Board Quick-Start Checklist Quick-Start Jumper SettingsJumper / Label Setting Configuration Switch S8 Quick-Start Switch SettingsSwitch / Label Setting Configuration Switch S1 Switch S5Global Configuration Settings Switch S5 Optional ConfigurationsGlobal Operating Configurations MII Address ConfigurationsMdio Routing Port Alternate Mdio Routing ConfigurationPHY Address Configuration Settings Switch S1 Jumper Setting DescriptionJumper Pin# Symbol Description Jtag Test SignalsExtended Temperature Operation with the LXT9785HE Jtag Test Signal DescriptionsLED Bits Program Description Direct Drive LED Configuration Settings RegisterLEDs Direct Drive LEDsLED Pulse Stretch Settings Register Bit Name Description Type DefaultInter Frame Status LEDs LXD9785 Pqfp MII Demo Board Power Fiber Board Revision A2 Board SchematicsMode Pqfp MII MII Ports 4 MIIPorts6and LXD9785 Pqfp Fpga for SS-SMII Fiber-to Fiber Ports 4 Fiber Ports 6 Board SS-SMII to MII Altera Clock Distribution Fpga Pqfp Demo Board with Fpga for SS-SMII MDIO0 and MDC0 Fix MDIO1 Bill of Materials LXD9785 Bill of Materials Fiber SS-SMIIReference Designator Description Manufacturer Part Number Ferrite Bead FAIR-RITE Panasonic ERJ-6ENF82R5V IC Logic Fairchild

249323-003, Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion specifications

The Intel 249323-003 demo board is an advanced platform designed for SS-SMII (Synchronous Serial - Synchronous Media Independent Interface) to MII (Media Independent Interface) conversion, utilizing FPGA technology. This demo board serves as a pivotal tool for developers and engineers in the field, facilitating the evaluation and testing of high-speed networking applications, particularly those involving fiber-optic communication.

At its core, the Intel 249323-003 is equipped with a robust FPGA that is capable of handling complex data processing tasks with high efficiency. The FPGA architecture allows for flexible configuration, enabling users to customize the interface as per their specific application requirements. This adaptability is crucial in developing solutions for various networking protocols, ensuring seamless integration across different mediums.

One of the standout features of the demo board is its support for fiber-optic connections, which are essential for high-speed data transmission over long distances. The board includes interfaces that allow for the connection of fiber transceivers, thereby facilitating faster communication speeds and improved bandwidth efficiency. This capability is particularly beneficial for applications in data centers, telecommunications, and other high-bandwidth scenarios.

Additionally, the Intel 249323-003 demo board showcases low latency performance, a critical characteristic for real-time applications. This feature is achieved through sophisticated design and optimization techniques that ensure quick data processing. The board also supports various data rates, making it versatile enough for different use cases.

Another important aspect is the board’s power consumption efficiency. By implementing advanced power management techniques, the Intel 249323-003 minimizes energy usage while maximizing performance, making it a cost-effective solution for developers looking to create sustainable applications.

In terms of connectivity, the demo board offers multiple I/O options, facilitating interaction with other devices and systems. This eases the development process, allowing engineers to prototype and test their designs rapidly.

In conclusion, the Intel 249323-003 demo board is a sophisticated and versatile platform for SS-SMII to MII conversion. With its powerful FPGA, support for fiber-optic interfaces, low latency, and efficient power management, it stands out as a vital resource for developers working on high-speed networking solutions. Whether for prototyping or extensive testing, this demo board equips engineers with the tools necessary to innovate and elevate their networking projects to new heights.
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