Intel 249323-003, Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion manual Fpga

Page 32

Document #: 249323

Revision #: 003

Rev. Date: January 24, 2002

32

Development Kit Manual

 

 

￿

 

 

￿

 

 

￿

 

 

￿

 

 

￿

 

 

 

 

 

 

 

￿;￿￿￿￿,￿

 

 

 

 

 

 

 

 

￿;￿￿￿￿,￿

 

 

 

 

 

 

 

 

 

￿￿/￿￿￿.

 

 

 

 

 

 

 

 

￿￿/￿￿￿.

 

 

 

 

 

 

 

 

 

 

￿%/<￿￿

 

 

 

 

 

 

 

 

￿%/<￿￿

 

 

 

 

 

￿

 

 

 

 

/￿￿￿/

 

 

 

 

 

 

 

 

/￿￿￿/

 

 

 

 

￿

 

 

 

 

 

 

 

 

7￿￿-

 

7￿￿-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,￿2

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

￿￿

￿￿￿+￿

 

 

￿￿￿+￿

￿￿

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

,￿￿

 

 

 

 

 

 

 

 

 

 

,￿3

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

￿￿3

 

 

￿￿3

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

,￿￿

 

 

 

 

 

 

 

 

 

￿￿￿￿

7￿+%.￿+*￿/+￿

7￿+%.￿+*￿/+￿

￿￿4￿

 

 

 

 

 

 

 

 

,￿￿

6￿￿￿￿￿

￿￿

￿￿

6￿￿￿￿￿

,￿4

 

 

 

 

 

 

 

 

 

6￿￿￿￿￿+￿

 

 

6￿￿￿￿￿+￿

 

 

 

 

 

￿￿1￿

￿￿￿

 

/.%8

 

￿￿￿￿

 

￿￿2

 

 

￿￿2

 

￿￿4￿

 

/.%8

 

￿4￿￿

￿￿￿

 

￿￿￿4

 

 

/.%8+￿

PORT 0

PORT 4

/.%8+￿

 

 

￿￿4￿

 

 

￿￿1￿

￿￿￿

￿7￿/￿,

 

 

4￿

4￿

 

 

￿7￿/￿,

￿4￿￿

￿￿￿

 

 

 

 

 

￿7￿/￿,+￿

￿7￿/￿,+￿

 

 

 

 

￿￿14

￿￿￿

 

￿￿￿￿

 

 

 

￿￿

 

 

￿￿

 

 

 

￿￿￿￿

 

￿4￿￿

￿￿￿

 

 

 

 

￿￿￿￿+￿

 

 

￿￿￿￿+￿

 

 

 

 

 

 

 

 

/￿￿

,￿1

￿,+￿￿

￿￿

 

 

￿￿

￿,+￿￿

,￿2

/￿￿

 

 

 

 

 

 

 

 

￿,+￿￿+￿

 

 

￿,+￿￿+￿

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

,￿￿

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

￿4￿

￿￿￿+￿

 

 

￿￿￿+￿

￿4￿

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

,1

 

 

 

 

 

 

 

 

 

 

,￿￿

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

￿4￿

 

 

￿4￿

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

,￿￿

 

 

 

 

 

 

 

 

 

￿￿￿3

7￿+%.￿+*￿/+￿

7￿+%.￿+*￿/+￿

￿￿￿￿

 

 

 

 

 

 

 

 

,￿￿

6￿￿￿￿￿

￿￿4

￿￿4

6￿￿￿￿￿

,￿￿

 

 

 

 

 

 

 

 

 

6￿￿￿￿￿+￿

 

 

6￿￿￿￿￿+￿

 

 

 

 

 

￿4￿3

￿￿￿

 

/.%8

 

￿￿￿1

 

￿￿￿

 

 

￿￿￿

 

￿￿￿2

 

/.%8

 

￿4￿￿

￿￿￿

 

￿￿￿￿

 

 

/.%8+￿

PORT 1

PORT 5

/.%8+￿

 

 

￿￿￿￿

 

 

￿4￿1

￿￿￿

￿7￿/￿,

 

 

￿￿1

￿￿1

 

 

￿7￿/￿,

￿4￿2

￿￿￿

 

 

 

 

 

￿7￿/￿,+￿

￿7￿/￿,+￿

 

 

 

 

￿4￿￿

￿￿￿

 

￿￿￿￿

 

 

 

￿￿3

 

 

￿￿3

 

 

 

￿￿￿￿

 

￿4￿￿

￿￿￿

 

 

 

 

￿￿￿￿+￿

 

 

￿￿￿￿+￿

 

 

 

 

 

 

 

 

/￿￿

,￿￿

￿,+￿￿

￿￿

 

 

￿￿

￿,+￿￿

,￿￿

/￿￿

 

 

 

 

 

 

 

 

￿,+￿￿+￿

 

 

￿,+￿￿+￿

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

,￿￿

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

￿￿￿

￿￿￿+￿

 

 

￿￿￿+￿

￿￿￿

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

,4

 

 

 

 

 

 

 

 

 

 

,￿4

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

￿￿￿

 

 

￿￿￿

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

,2

 

 

 

 

 

￿

 

 

 

￿￿￿￿

7￿+%.￿+*￿/+￿

7￿+%.￿+*￿/+￿

￿￿￿￿

 

 

 

￿

 

 

 

,￿2

6￿￿￿￿￿

￿4￿

￿4￿

6￿￿￿￿￿

,3

 

 

 

 

 

 

 

 

 

 

 

￿4￿￿

￿￿￿

 

/.%8

 

￿￿￿4

 

￿4￿

6￿￿￿￿￿+￿

 

 

6￿￿￿￿￿+￿

￿4￿

 

￿￿￿￿

 

/.%8

 

￿4￿￿

￿￿￿

 

￿￿￿3

 

 

/.%8+￿

PORT 2

PORT 6

/.%8+￿

 

 

￿￿￿￿

 

 

￿4￿4

￿￿￿

￿7￿/￿,

 

 

￿44

￿44

 

 

￿7￿/￿,

￿4￿￿

￿￿￿

 

 

 

 

 

￿7￿/￿,+￿

￿7￿/￿,+￿

 

 

 

 

￿4￿3

￿￿￿

 

￿￿￿￿

 

 

 

￿￿4

 

 

￿￿4

 

 

 

￿￿￿￿

 

￿4￿￿

￿￿￿

 

 

 

 

￿￿￿￿+￿

 

 

￿￿￿￿+￿

 

 

 

 

 

 

 

 

/￿￿

,￿3

￿,+￿￿

￿￿3

 

 

￿￿3

￿,+￿￿

,￿

/￿￿

 

 

 

 

 

 

 

 

￿,+￿￿+￿

 

 

￿,+￿￿+￿

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

,￿￿

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

￿￿2

￿￿￿+￿

 

 

￿￿￿+￿

￿￿2

￿￿/ ￿￿￿￿￿￿.￿￿￿￿￿￿￿￿￿

,￿

 

 

 

 

 

 

 

 

 

 

,￿1

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

￿￿￿

 

 

￿￿￿

7￿￿￿￿￿%.￿￿/￿￿*￿/.￿

,￿

 

 

 

 

 

 

 

 

 

￿￿￿1

7￿+%.￿+*￿/+￿

7￿+%.￿+*￿/+￿

￿￿￿￿

 

 

 

 

 

 

 

 

,￿￿

6￿￿￿￿￿

￿￿￿

￿￿￿

6￿￿￿￿￿

,￿

 

 

 

 

 

 

 

 

 

6￿￿￿￿￿+￿

 

 

6￿￿￿￿￿+￿

 

 

 

 

 

￿4￿1

￿￿￿

 

/.%8

 

￿￿4￿

 

￿￿￿

 

 

￿￿￿

 

￿￿￿￿

 

/.%8

 

￿￿1￿

￿￿￿

 

￿￿4￿

 

 

/.%8+￿

PORT 3

PORT 7

/.%8+￿

 

 

￿￿￿2

 

 

￿4￿￿

￿￿￿

￿7￿/￿,

 

 

￿￿￿

￿￿￿

 

 

￿7￿/￿,

￿￿1￿

￿￿￿

 

 

 

 

 

￿7￿/￿,+￿

￿7￿/￿,+￿

 

 

 

 

￿4￿￿

￿￿￿

 

￿￿￿￿

 

 

 

￿￿￿

 

 

￿￿￿

 

 

 

￿￿￿￿

 

￿￿12

￿￿￿

 

 

 

 

￿￿￿￿+￿

 

 

￿￿￿￿+￿

 

 

 

 

 

 

 

 

/￿￿

,￿3

￿,+￿￿

￿￿4

 

 

￿￿4

￿,+￿￿

,￿

/￿￿

 

 

 

 

 

 

 

 

￿,+￿￿+￿

 

 

￿,+￿￿+￿

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-%￿

 

 

 

/￿￿

 

 

 

 

 

 

 

 

 

 

/￿￿

 

 

 

-%￿

 

 

 

 

 

 

 

￿￿￿￿8￿￿￿>￿￿￿￿0￿+

+ :..

￿￿￿￿8￿￿￿>￿￿￿￿0￿+ +

:..

 

 

 

 

 

 

 

￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

￿

￿

￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

￿￿￿￿￿

 

 

 

 

 

 

 

 

 

 

 

￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

￿!￿

￿"#￿$￿￿￿￿%￿$￿￿￿

 

￿￿&

 

 

 

 

 

 

￿

.%￿￿￿0￿￿￿:￿￿ ￿￿￿7 ￿/￿￿=

 

￿￿

 

 

 

 

 

 

 

 

 

 

 

 

 

 

￿￿￿￿'

￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿

(￿￿￿ ￿4 ") ￿￿

 

 

￿

￿

￿

￿

 

 

￿

Figure 17. Inter-Frame Status

LXD9785 PQFP Demo Board with

LEDs

FPGA

 

for SS-SMII (Fiber)-to

 

-MII

 

Conversion

Image 32
Contents Development Kit Manual JanuaryDocument # Revision # Rev. Date January 24 Contents Tables Revision History Date Revision DescriptionPage Features General DescriptionLXD9785 Pqfp MII Demo Board Fiber Register Configuration IntroductionOverview Equipment RequirementsTypical Setup Typical Test SetupLXD9785/9785E SS-SMII Fiber Demo Board Jumper / Label Setting Configuration Quick-Start ChecklistQuick-Start Jumper Settings Quick-Start Switch Settings Switch / Label Setting Configuration Switch S1Switch S5 Switch S8Optional Configurations Global Operating ConfigurationsMII Address Configurations Global Configuration Settings Switch S5Alternate Mdio Routing Configuration PHY Address Configuration Settings Switch S1Jumper Setting Description Mdio Routing PortJtag Test Signals Extended Temperature Operation with the LXT9785HEJtag Test Signal Descriptions Jumper Pin# Symbol DescriptionDirect Drive LED Configuration Settings Register LEDsDirect Drive LEDs LED Bits Program DescriptionInter Frame Status LEDs LED Pulse Stretch Settings RegisterBit Name Description Type Default Board Schematics LXD9785 Pqfp MII Demo Board Power Fiber Board Revision A2Mode Pqfp MII MII Ports 4 MIIPorts6and LXD9785 Pqfp Fpga for SS-SMII Fiber-to Fiber Ports 4 Fiber Ports 6 Board SS-SMII to MII Altera Clock Distribution Fpga Pqfp Demo Board with Fpga for SS-SMII MDIO0 and MDC0 Fix MDIO1 Reference Designator Description Manufacturer Part Number Bill of MaterialsLXD9785 Bill of Materials Fiber SS-SMII Ferrite Bead FAIR-RITE Panasonic ERJ-6ENF82R5V IC Logic Fairchild

249323-003, Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion specifications

The Intel 249323-003 demo board is an advanced platform designed for SS-SMII (Synchronous Serial - Synchronous Media Independent Interface) to MII (Media Independent Interface) conversion, utilizing FPGA technology. This demo board serves as a pivotal tool for developers and engineers in the field, facilitating the evaluation and testing of high-speed networking applications, particularly those involving fiber-optic communication.

At its core, the Intel 249323-003 is equipped with a robust FPGA that is capable of handling complex data processing tasks with high efficiency. The FPGA architecture allows for flexible configuration, enabling users to customize the interface as per their specific application requirements. This adaptability is crucial in developing solutions for various networking protocols, ensuring seamless integration across different mediums.

One of the standout features of the demo board is its support for fiber-optic connections, which are essential for high-speed data transmission over long distances. The board includes interfaces that allow for the connection of fiber transceivers, thereby facilitating faster communication speeds and improved bandwidth efficiency. This capability is particularly beneficial for applications in data centers, telecommunications, and other high-bandwidth scenarios.

Additionally, the Intel 249323-003 demo board showcases low latency performance, a critical characteristic for real-time applications. This feature is achieved through sophisticated design and optimization techniques that ensure quick data processing. The board also supports various data rates, making it versatile enough for different use cases.

Another important aspect is the board’s power consumption efficiency. By implementing advanced power management techniques, the Intel 249323-003 minimizes energy usage while maximizing performance, making it a cost-effective solution for developers looking to create sustainable applications.

In terms of connectivity, the demo board offers multiple I/O options, facilitating interaction with other devices and systems. This eases the development process, allowing engineers to prototype and test their designs rapidly.

In conclusion, the Intel 249323-003 demo board is a sophisticated and versatile platform for SS-SMII to MII conversion. With its powerful FPGA, support for fiber-optic interfaces, low latency, and efficient power management, it stands out as a vital resource for developers working on high-speed networking solutions. Whether for prototyping or extensive testing, this demo board equips engineers with the tools necessary to innovate and elevate their networking projects to new heights.