Intel Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion, 249323-003 Clock Distribution

Page 31

Rev. Date: January 24,	Document #: 249323 Revision #: 003
2002

Development Kit Manual

31

A

B

C

D

E

3

SECTION

SECTION

VCC_EXT

**NOTE**

DURING

LAYOUT THESE

NETS MUST

HAVE

CONTROLLED

IMPEDANCES OF 50 OHMS

FB8

Ferrite Bead

4

4

VCC_EXT

Y1

C156

C157

JP14

1

NC

VCC

14

VCCX

0.1uF

0.01uF

PLD2_TCK

1

2

PLD2_TDO

3

4

PLD2_TMS

5

6

GND

PLD2_TDI

7

8

9

10

R454

7

GND

OUT

8

HEADER 5X2

GND

50 1%

GND

125 MHzCRYSTAL OSC

J4

SMA(5 PIN)

3

3

GND

DISTRIBUTE

VCC_EXT

TP71

TP69

TP70

TP68

TP66

TP67

TP65

TP62

TP63

TP64

C346

C347

C348

C349

1

1

1

1

1

1

1

1

1

1

Y2

0.01uF

0.1uF

0.01uF

0.1uF

C350

C351

1

NC

VCC

14

VCCX

0.1uF

0.01uF

GND

U46

GND

9 29 17 41

GND

R732

VCCIO VCCIO VCCINT VCCINT

7

GND

OUT

8

50 1%

37

CLK1

2

GND

VCC_EXT

40

CLK2

CLK_OUT0

15

R455

50 1%

REF_CLK_0

2

125 MHzCRYSTAL OSC

18

R460

50 1%

REF_CLK_1

CLK_OUT1

19

R456

50 1%

REF_CLK_2

CLK_OUT2

SECTION

42

20

R461

50 1%

REF_CLK_3

SECTION

CLK_OUT3

R733

R734

R735

R736

J5

1K

1K

1K

1K

PLD2_TDI

1

TDI

PLD2_TMS

7

TMS

PLD2_TCK

26

39

TCK

INPUT2

SMA(5 PIN)

PLD2_TDO

32

38

TDO

GNDIO GNDIO GNDINT GNDINT

INPUT1

GND

REF_CLK_0

REF_CLK_0

3

REF_CLK_1

4 24 16 36

REF_CLK_1

3

GND

REF_CLK_2

REF_CLK_2

13

EPM7032AETC44-4_CLK_DISTR

REF_CLK_3

REF_CLK_3

13

GND

1

1

Title

LXD9785 SS/SMII MII FX DV BOARD

Size

Document Number

Rev

B

CLOCK DISTRIBUTION

A2

Date:

Wednesday, February 21, 2001

Sheet

14

of 18

A

B

C

D

E

Figure 16. Clock Distribution	LXD9785 PQFP
	Demo Board with FPGA for SS-SMII
	(Fiber)-to
	-MII
	Conversion

Image 31

Contents January Development Kit ManualDocument # Revision # Rev. Date January 24 Contents Tables Date Revision Description Revision HistoryPage General Description FeaturesLXD9785 Pqfp MII Demo Board Equipment Requirements Fiber Register ConfigurationIntroduction OverviewTypical Test Setup Typical SetupLXD9785/9785E SS-SMII Fiber Demo Board Quick-Start Jumper Settings Quick-Start ChecklistJumper / Label Setting Configuration Switch S8 Quick-Start Switch SettingsSwitch / Label Setting Configuration Switch S1 Switch S5Global Configuration Settings Switch S5 Optional ConfigurationsGlobal Operating Configurations MII Address ConfigurationsMdio Routing Port Alternate Mdio Routing ConfigurationPHY Address Configuration Settings Switch S1 Jumper Setting DescriptionJumper Pin# Symbol Description Jtag Test SignalsExtended Temperature Operation with the LXT9785HE Jtag Test Signal DescriptionsLED Bits Program Description Direct Drive LED Configuration Settings RegisterLEDs Direct Drive LEDsBit Name Description Type Default LED Pulse Stretch Settings RegisterInter Frame Status LEDs LXD9785 Pqfp MII Demo Board Power Fiber Board Revision A2 Board SchematicsMode Pqfp MII MII Ports 4 MIIPorts6and LXD9785 Pqfp Fpga for SS-SMII Fiber-to Fiber Ports 4 Fiber Ports 6 Board SS-SMII to MII Altera Clock Distribution Fpga Pqfp Demo Board with Fpga for SS-SMII MDIO0 and MDC0 Fix MDIO1 LXD9785 Bill of Materials Fiber SS-SMII Bill of MaterialsReference Designator Description Manufacturer Part Number Ferrite Bead FAIR-RITE Panasonic ERJ-6ENF82R5V IC Logic Fairchild