Contents |
| |
Tables |
| |
1 | 12 | |
2 | 13 | |
3 | Global Configuration Settings (Switch S5) | 14 |
4 | Global Configuration Settings (Switch S8) | 14 |
5 | PHY Address Configuration Settings (Switch S1) | 15 |
6 | MDIO Routing (Port 0) | 15 |
7 | JTAG Test Signal Descriptions | 16 |
8 | Direct Drive LED Configuration Settings (Register 20) | 17 |
9 | LED Pulse Stretch Settings (Register 20) | 18 |
10 | LXD9785 Bill of Materials (Fiber - | 36 |
ivLXD9785 PQFP Demo Board with FPGA for
Document #: 249323
Revision #: 003
Rev. Date: January 24, 2002