Intel TE430VX manual Chipset, Sdram, Second Level Cache, 1 82430VX System Controller TVX

Motherboard Description

1.5.1.2SDRAM

Synchronous Dynamic Random Access Memory, (SDRAM) is designed to improve main memory performance. SDRAM is synchronous to the memory clock unlike standard Fast Page DRAM, or EDO DRAM. All the timing is dependent on the number of memory clock cycles. This makes the timing design simpler and makes a faster memory speed easier to achieve. Discrete SDRAM components must meet the 66 MHz PC SDRAM Specification version 1.0 to function correctly.

1.5.2Second Level Cache

The Pentium processor's internal cache can be complemented by a second level cache using high- performance Pipelined Burst SRAM with GWE (Global Write Enabled) or Asynchronous Cache.

One factory option is an integrated 256 KB direct mapped write-back second level cache implemented with two 32k x 32 Pipeline Burst SRAM devices that take advantage of the Global Write Enable pin. A 5v 8 KB x 8 external Tag SRAM provides caching support for up to 64 MB of system memory.

A second factory option is a Type 1 CELP connector, specified by Intel’s COAST Module Specification version 3.0. The Type 1 CELP connector has a keying “hip” located at one end of the connector. This connector allows the use of both a GWE PBSRAM COAST module, and a GWE Asynchronous COAST module. The GWE Asynchronous modules must be built for Intel’s 82430VX designs and are not interchangeable with Asynchronous modules built for 82430FX designs. The reason for this incompatibility is the additional logic added to the 82430VX modules to account for the GWE functionality built into the chipset.

1.6 Chipset

The Intel 82430VX PCIset consists of the 82430VX System Controller (TVX), two Data Paths (TDX) and one 82371SB PCI ISA/IDE Xcelerator (PIIX3) bridge chip.

1.6.182430VX System Controller (TVX)

The 82430VX TVX provides all control signals necessary to drive a second level cache and the DRAM array, including multiplexed address signals. The TVX also controls system access to memory and generates snoop controls to maintain cache coherency. The TVX comes in a 208-pin QFP package that features:

∙CPU interface control

∙Integrated L2 write-back cache controller

⎯Pipeline Burst SRAM

⎯256 or 512 KB direct-mapped

∙Integrated DRAM controller

⎯64 bit path to memory

⎯Support for SDRAM and EDO DRAM

⎯8 MB to 128 MB main memory

∙Fully synchronous PCI bus interface

⎯25/30/33 MHz

⎯PCI to DRAM > 100 Mbytes/sec

⎯Up to 4 PCI masters in addition to the PIIX3 and IDE

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