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POST (hex) |
| Description |
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1Dh | Initial EARLY_PM_INIT switch. |
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1Fh | Load keyboard matrix (notebook platform) |
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21h | HPM initialization (notebook platform) |
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23h | 1. | Check validity of RTC value: |
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| e.g. a value of 5Ah is an invalid value for RTC minute. |
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| 2. | Load CMOS settings into BIOS stack. If CMOS checksum fails, |
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| use default value instead. |
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| 3. | Prepare BIOS resource map for PCI & PnP use. If ESCD is |
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| valid, take into consideration of the ESCD¡¦s legacy information. |
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| 4. | Onboard clock generator initialization. | Disable respective clock |
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| resource to empty PCI & DIMM slots. |
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| 5.Early PCI initialization: |
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| into C000:0. |
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25h | PCI Bus Initialization |
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26h | Init clock Generator |
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27h | Initialize INT 09 buffer |
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29h | 1. | Program CPU internal MTRR (P6 & PII) for |
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| 2. | Initialize the APIC for Pentium class CPU. |
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| 3. Program early chipset according to CMOS setup. Example: onboard IDE |
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| controller. |
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| 4. Measure CPU speed |
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2Bh | Invoke video BIOS. |
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2Dh | 1. | Initialize |
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| 2. | Put information on screen display, including Award title, CPU type, |
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| CPU speed |
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33h | Reset keyboard except Winbond 977 series Super I/O chips. |
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3Ch | Test 8254 |
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3Eh | Test 8259 interrupt mask bits for channel 1. |
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40h | Test 8259 interrupt mask bits for channel 2. |
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43h | Test 8259 functionality. |
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47h | Initialize EISA slot |
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49h | 1. Calculate total memory by testing the last double word of each 64K page. |
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| 2. | Program write allocation for AMD K5 CPU 64K page. |
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4Eh | 1. Program MTRR of M1 CPU |
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| 2. | Initialize L2 cache for P6 class CPU & program CPU with proper |
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| cacheable range. |
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| 3. | Initialize the APIC for P6 class CPU. |
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| 4. | On MP platform, adjust the cacheable range to smaller one in case the |
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| cacheable ranges between each CPU are not identical. |
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- 105 - | Appendix |