Oki MSM80C154S, MSM83C154S manual Power control register Pcon, Interrupt signal, CPU is reset

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MSM80C154S/83C154S

 

 

 

 

 

 

 

 

¡ Semiconductor

Power control register (PCON)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NAME

ADDRESS

MSB

 

 

 

 

 

 

 

 

 

 

LSB

7

6

 

5

 

4

3

 

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON

87H

SMOD

HPD

 

RPD

 

—

GF1

 

GF0

PD

 

IDL

BIT LOCATION

FLAG

 

 

 

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.0

IDL

IDLE mode is set when this bit is set to "1". CPU operations are stopped when

 

 

IDLE mode is set, but XTAL1•2, timer/counters 0, 1 and 2, the interrupt circuits,

 

 

and the serial port remain active. IDLE mode is cancelled when the CPU is reset

 

 

or when an interrupt is generated.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.1

PD

PD mode is set when this bit is set to "1". CPU operations and XTAL1•2 are

 

 

stopped when PD mode is set. PD mode is cancelled when the CPU is reset or

 

 

when an interrupt is generated.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.2

GF0

General purpose bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.3

GF1

General purpose bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.4

—

Reserved bit. The output data is "1", if the bit is read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.5

RPD

This bit is used to specify cancellation of CPU power down mode (IDLE or PD) by an

 

 

interrupt signal.

 

 

 

 

 

 

 

 

 

 

 

 

Power-down mode cannot be cancelled by an interrupt signal if the interrupt is not

 

 

enabled by IE (interrupt enable register) when this bit is "0".

 

 

 

 

 

 

If the interrupt flag is set to "1" by an interrupt request signal when this bit is

 

 

"1" (even if interrupt is disabled), the program is executed from the next address

 

 

of the power-down-mode setting instruction.

 

 

 

 

 

 

 

The flag is reset to "0" by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON.6

HPD

The hard power-down setting mode in enabled when this bit is set to "1".

 

 

 

 

If the level of the power failure detect signal applied to the HPDI pin (pin 3.5)

 

 

is changed from "1" to "0" when this bit is "1", XTAL1•2 oscillation is stopped and

 

 

the system is put into hard power down mode. HPD mode is cancelled when the

 

 

CPU is reset.

 

 

 

 

 

 

 

 

 

 

PCON.7

SMOD

When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of

 

 

the serial port, this bit has the following functions.

 

 

 

 

 

 

 

The serial port operation clock is reduced by 1/2 when the bit is "0" for delayed

 

 

processing. When the bit is "1", the serial port operation clock is normal

 

 

 

 

for faster processing.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Contents Features General Description¡SemiconductorSemiconductor MSM80C154S/83C154S Cmos 8-bit MicrocontrollerMSM80C154S/83C154S ¡ SemiconductorSignal TIMER/COUNTER 0 Interrupt2PORT Address DecoderPIN Configuration TOP View Pin Plastic DIPPsen Reset Pin Plastic QFP44 P1.4 P1.5 P1.6 P1.7 25 P2.7 24 P2.6 23 P2.5 P2.4Pin Plastic Tqfp Pin Plastic QFJ 35 EA P3.0/RXD 34 NC 33 ALE P3.1/TXDXTAL1 XTAL2 19 P3.7/RD 18 P3.6/WR PIN Descriptions MSM80C154S/83C154S¡ SemiconductorALE ¡ SemiconductorMSM80C154S/83C154S XTAL1XTAL2 Diagram of Special Function Registers RegistersSpecial Function Registers Timer mode register Tmod GatePower control register Pcon Interrupt signalCPU is reset Timer control register Tcon Interrupt request flag for external interruptTcon TR1 TF0 TR0 IE1 IT1 IE0 IT0Serial port control register Scon RENMode Interrupt enable register IE Interrupt control bit for serial portReserved bit. The output data is 1 if the bit is read Overall interrupt control bitPriority is assigned when bit is Interrupt priority register IPPriority interrupt circuit control bit PCT PT2 PT1 PX1 PT0 PX0Bank When this bit is set to Control register IoconIZC Received at a serial portTimer 2 control register T2CON Memory Maps Program AreaHEX 0FF Addressingindirectregister BIT RAMBANK3 BANK2MSM80C154S/83C154S Diagram of Internal Data Memory RAM 0FFH2FH 0FHAbsolute Maximum Ratings Recommended Operating ConditionsElectrical Characteristics DC CharacteristicsPort 0, ALE, Psen Maximum power supply current normal operation ICC mA Maximum power supply current idle mode ICC mAOutput High Voltage Port 1, 2 Logical 0 Input Current VI=0.1 Logical 1 Output CurrentVO=0.1 Port 1, 2 Logical 1 to 0 Transition 285 Measuring circuits InputOutput ALE Signal Width Address Setup TimeFalling Edge Psen Signal Width To ALE Falling Edge Address Hold TimeExternal program memory read cycle PORT0Instr External data memory access AC characteristics External data memory read cycle External data memory write cycleSerial port I/O Extension Mode AC characteristics Parameter Symbol Min Max UnitALE Shift Clock Input DataAC Characteristics Measuring Conditions External Oscillator SignalXTAL1 external clock input waveform conditions External Clock Drive WaveformBasictiming TimingDiagram 294
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