Oki MSM83C154S, MSM80C154S manual External data memory access AC characteristics

¡ Semiconductor					MSM80C154S/83C154S
(3) External data memory access AC characteristics
			VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C
PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load
			Variable clock from*1
Parameter	Symbol			1 to 24 MHz			Unit
			Min.			Max.
XTAL1, XTAL2 Oscillator Cycle	tCLCL		41.7			1000	ns
ALE Signal Width	tLHLL		2tCLCL-40			—	ns
Address Setup Time	tAVLL		1tCLCL-15			—	ns
(to ALE Falling Edge)
Address Hold Time	tLLAX		1tCLCL-35			—	ns
(from ALE Falling Edge)
RD Signal Width	tRLRL		6tCLCL-100			—	ns
WR Signal Width	tWLWH		6tCLCL-100			—	ns
RAM Data Read Time	tRLDV		—			5tCLCL-105	ns
(from RD Signal Falling Edge)
RAM Data Read Hold Time	tRHDX		0			—	ns
(from RD Signal Rising Edge)
Data Bus Floating Time	tRHDZ		—			2tCLCL-70	ns
(from RD Signal Rising Edge)
RAM Data Read Time	tLLDV		—			8tCLCL-100	ns
(from ALE Signal Falling Edge)
RAM Data Read Time	tAVDV		—			9tCLCL-105	ns
(from Address Output)
RD/WR Output Time from ALE	tLLWL		3tCLCL-40			3tCLCL+40	ns
Falling Edge		*2	3tCLCL-100
RD/WR Output Time from Address	tAVWL		4tCLCL-70			—	ns
Output
WR Output Time from Data Output	tQVWX		1tCLCL-40			—	ns
Time from Data to WR Rising Edge	tQVWH		7tCLCL-105			—	ns
Data Hold Time	tWHQX		2tCLCL-50			—	ns
(from WR Rising Edge)
Time from to Address Float RD	tRLAZ		0			—	ns
Output
Time from RD/WR Rising Edge to	tWHLH		1tCLCL-30			1tCLCL+40	ns
ALE Rising Edge					*2	1tCLCL+100

*1 The variable check is from 0 to 24 MHz when the external check is used. *2 For 2.2£VCC<4 V

289