Functional Description | CPU Bus Interface |
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Each of the device buses are de-coupled from each other, enabling concurrent operation of the CPU bus, PCI buses and access to SDRAM. Refer to the GT-64260B System Controller for PowerPC Processors Data Sheet, listed in Appendix C, Related Documentation, for more details.
2.6.1CPU Bus Interface
The GT-64260B supports MPX or 60x bus mode operation. The MVME5500 board has jumper/build option resistors to select either operating mode at power-up.
2.6.2Memory Controller Interface
The GT-64260B can access up to four banks of SDRAM for a total of 1GB of SDRAM memory. The memory bus is capable of operating up to 133 MHz.
The MVME5500 board has two banks on board and a connector for an expansion mezzanine board with two additional banks.
2.6.3Interrupt Controller
The MVME5500 uses the interrupt controller integrated into GT-64260B to manage the GT- 64260B internal interrupts, as well as the external interrupt requests. The external interrupt sources include the following:
zOn-board PMC interrupts
zLAN interrupts
zVME interrupts
zRTC interrupt
zWatchdog timer interrupts
zAbort switch interrupt
zExternal UART interrupts
The interrupt controller provides up to seven interrupt output pins for various interrupt functions. For additional details regarding the external interrupt assignments, refer to the MVME5500 Single-Board Computer Programmer’s Reference Guide.
2.6.4I2C Serial Interface and Devices
A two-wire serial interface for the MVME5500 board is provided by a master/slave capable I2C serial controller integrated into the GT-64260B device. The I2C serial controller provides two basic functions. The first function is to optionally provide GT-64260B register initialization following a reset. The GT-64260B can be configured (by setting jumper J17) to automatically read data out of a serial EEPROM following a reset and initialize any number of internal registers. In the second function, the controller is used by the system software to read the contents of the VPD EEPROM contained on the MVME5500 board, along with the SPD EEPROM(s), to further initialize the memory controller and other interfaces.
40 | MVME55006E Single-Board Computer Installation and Use (6806800A37D) |
