Sun Microsystems Interface Adapter manual Clock Signal Inversion

By inverting the data signal with HDLC framing on both ends of a link, the HDLC zero insertion algorithm becomes a ones insertion algorithm. This guarantees that in any set of seven bits, at least one bit will be a one. Thus, the HDLC data stream meets the density requirements of North American T1 lines without sacrificing any bandwidth.

Clock Signal Inversion

The need to invert clock lines is separate from the need to invert data lines. Most computer, modem, and terminal vendors adhere to an industry standard specification known as RS-334. This specification defines the relationship between a data bit and a reference clock on a synchronous serial link. The specification also dictates that a device should transmit data with reference to the rising edge of the clock signal, and that data should be received with reference to the falling edge of the clock signal.

When using long cables or cables not carrying a clock signal, a phase shift might occur causing a high number of errors. In such cases, inverting the clock signal may correct the phase shift. You may also need to invert the clock signal when connecting a SunHSI/U port to equipment not adhering to the RS-334 standard.

Appendix C T1 Inverted Data and Clock Signals 37