6.2 Interrupt Status Register
The DS-200/300 is equipped with an Interrupt Status Register (ISR) which can be used to simplify the servicing of shared interrupts. This register is located at [base address+7] along with the Options Register. Like the OR, the SP jumper must be removed to access the ISR. To further indicate an access to this register, the DLAB bit in the LCR of the UART must be set to 0. The ISR is read-only.
When a hardware interrupt occurs, reading the ISR will return the interrupt status of both ports on the DS-200/300, as shown in Figure 14. Individual bits are cleared as the interrupting ports are serviced. The interrupt service routine must ensure that the ISR reads zero before exiting, or the DS-200/300 will be unable to signal subsequent interrupts.
BIT | DESCRIPTION |
| |
7 (MSB) | 0 (not used) |
| |
6 | 0 (not used) |
| |
5 | 0 (not used) |
4 | 0 (not used) |
| |
3 | 0 (not used) |
| |
2 | 0 (not used) |
| |
1 | Serial 1 --- 1 if interrupt pending |
| |
0 | Serial 0 --- 1 if interrupt pending |
Figure 14 --- Interrupt Status Register contents