Quatech DS-102 user manual Modem Control Register, Are being used

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MODEM CONTROL REGISTER

This register is located at I/O address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are DTR (Data Terminal Ready) and RTS (Request To Send). It is also possible to place the UART in a loopback mode for testing. Finally, the user-defined outputs OUT1 and OUT2 are controlled from this register.

The DS-102 handles the OUT1 and OUT2 signals in the manner appropriate for maintaining compatibility with standard PC serial ports:

 

The OUT1 output is not connected.

 

The OUT2 output is used to globally enable interrupts to

 

 

the computer. It should be active at all times if interrupts

 

 

are being used.

 

 

 

BIT

 

DESCRIPTION

 

 

 

7

 

0 --- reserved

 

 

 

6

 

0 --- reserved

 

 

 

5

 

0 --- reserved

 

 

 

4

 

LOOP --- Loopback enable:

 

 

When set (logic 1), the transmitter shift register is connected directly to the

 

 

receiver shift register. The MODEM control inputs are internally connected

 

 

to the MODEM control outputs and the outputs are forced to the inactive

 

 

state. All characters transmitted are immediately received to verify

 

 

transmit and receive data paths. Transmitter and receiver interrupts still

 

 

operate normally. MODEM control interrupts are available but are now

 

 

controlled through the MODEM control register.

 

 

 

3

 

OUT2 --- Output 2:

 

 

When this bit is set (logic 1), the OUT2 output is forced active to a logic 0.

 

 

When cleared (logic 0), the OUT2 output is forced inactive to a logic 1.

 

 

Used for interrupt enable on the DS-102.

 

 

 

2

 

OUT1 --- Output 1:

 

 

When this bit is set (logic 1), the OUT1 output is forced active to a logic 0.

 

 

When cleared (logic 0), the OUT1 output is forced inactive to a logic 1.

 

 

Not connected on the DS-102.

 

 

 

1

 

RTS --- Request to send:

 

 

When this bit is set (logic 1), the RTS output is forced active to a logic 0.

 

 

When cleared (logic 0), the RTS output is forced inactive to a logic 1.

 

 

 

0

 

DTR --- Data terminal ready:

 

 

When this bit is set (logic 1), the DTR output is forced active to a logic 0.

 

 

When cleared (logic 0), the DTR output is forced inactive to a logic 1.

 

 

 

 

 

Figure 21 --- Modem Control Register bit definitions

20

Quatech DS-102 User's Manual

Image 26
Contents DS-102 Page Table of Contents IV. Setting Interrupt Levels IrqsVII. Specifications VIII. Troubleshooting External Connections VI. Serial Port Functional DescriptionPage Date of Purchase Model Number Page General Information Port Address IRQ Enabled ? Diagram of DS-102 Setting the address Examination of a serial port base addressSerial 1 uses SW1 Serial 2 uses SW2 Enabling or disabling ports Recommended addresses for serial portsThis page intentionally left blank Serial Interrupt Sharing Channel Connection Interrupt OperationExternal Connections J7 -- Serial J8 -- Serial DS-102 connector definitions for RS-232-C This page intentionally left blank VI. Serial Port Functional Description Accessing the Serial Port registers DlabInterrupt Enable Register Interrupt Identification RegisterInterrupt Identification Register bit definitions Fifo Control Register 16550 only RXT0Line Control Register Stkp EPS PEN ParityModem Control Register Are being usedLine Status Register Line Status Register bit definitionsModem Status Register Scratchpad RegisterFifo Interrupt Mode Operation 16550 Uart only When the receiver Fifo and receiver interrupts are enabledFifo polled mode operation 16550 Uart only Factory default Baud Rate Selection026 VII. Specifications 16450 16550 optionalComputer will not boot up

DS-102 specifications

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