Quatech DS-102 user manual Modem Status Register, Scratchpad Register

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MODEM STATUS REGISTER

This register is located at I/O address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem. It allows the current states of "modem control signals" to be sensed. These signals include the DCD (Data Carrier Detect), RI (Ring Indicator), DSR (Data Set Ready), and CTS (Clear To Send).

The Modem Status Register also provides change information for each of these signals. When a modem control signal changes state, the appropriate change bit is set to logic 1. The change bits (3, 2, 1, and 0) are reset to logic 0 whenever the Modem Status Register is read.

A modem status interrupt is generated whenever any of bits 3, 2, 1 or 0 is set by the UART to a logic 1.

BIT	DESCRIPTION

7	DCD --- Data carrier detect:
	Complement of the DCD input.

6	RI --- Ring indicator:
	Complement of the RI input.

5	DSR --- Data set ready:
	Complement of the DSR input.

4	CTS --- Clear to send:
	Complement of the CTS input.

3	DDCD --- Delta data carrier detect:
	Indicates the Data Carrier Detect input has changed state.
	Cleared when this register is read.

2	TERI --- Trailing edge ring indicator:
	Indicates the Ring Indicator input has changed from a low to a high
	state.
	Cleared when this register is read.

1	DDSR --- Delta data set ready:
	Indicates the Data Set Ready input has changed state.
	Cleared when this register is read.

0	DCTS --- Delta clear to send:
	Indicates the Clear to Send input has changed state.
	Cleared when this register is read.

	Figure 23 --- Modem Status Register bit definitions

SCRATCHPAD REGISTER

This register is located at I/O address [base+7]. It is not used by the 16450 or 16550. It may be used by the programmer for temporary data storage. The Scratchpad Register is eight bits wide and can be read or written.

22	Quatech DS-102 User's Manual

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Contents DS-102 Page IV. Setting Interrupt Levels Irqs VII. Specifications VIII. TroubleshootingTable of Contents External Connections VI. Serial Port Functional DescriptionPage Date of Purchase Model Number Page General Information Port Address IRQ Enabled ? Diagram of DS-102 Setting the address Examination of a serial port base addressSerial 1 uses SW1 Serial 2 uses SW2 Enabling or disabling ports Recommended addresses for serial portsThis page intentionally left blank Serial Interrupt Sharing Channel Connection Interrupt OperationExternal Connections J7 -- Serial J8 -- Serial DS-102 connector definitions for RS-232-C This page intentionally left blank VI. Serial Port Functional Description Accessing the Serial Port registers DlabInterrupt Enable Register Interrupt Identification RegisterInterrupt Identification Register bit definitions Fifo Control Register 16550 only RXT0 Line Control Register Stkp EPS PEN ParityModem Control Register Are being usedLine Status Register Line Status Register bit definitionsModem Status Register Scratchpad RegisterFifo Interrupt Mode Operation 16550 Uart only When the receiver Fifo and receiver interrupts are enabledFifo polled mode operation 16550 Uart only Factory default Baud Rate Selection026 VII. Specifications 16450 16550 optionalComputer will not boot up