Arcam AV8 ADC Refer to circuit diagram L896 Sheet 2 , DAC Refer to circuit diagram L896 Sheets 3,4,5,6 , DSP Refer to circuit diagram L896 Sheet 7

SK1000
Pin1 P18V
Pin2 AGND
Pin3 N18V
Pin4 P21V
Pin5 AGN
Pin6 N21V
SK1001
Pin1 P12V
Pin2 DGND
Pin3 N12V
Pin4 DGND
Pin5 P5V
Pin6 DGND
Pin7 P3V3
Pin8 DGND
SK1002
Pin1 PSU SYNC
Pin2 PSU GOOD
Pin3 PSU KILL
Pin4 DGND
SK1003
Pin1 P36VF1
Pin2 0VF1
Pin3 P36VSET
Pin4 P5VF2
Pin5 OVF2
Pin6 P5VF2SET
Pin7 N/C
ADC
Refer to circuit diagram L896 Sheet 2
The signals to the ADC are c onverted to balanced by the th r ee
opamps th at also c o rrect the level to the input of the ADC so
that 2VRMS on the input of the first opamp provides a full-scale
input to the ADC. 2.45V p-p (Note: not RMS)
A bias is added to the incoming signal so that it can be input to
the ADC ana logue section wh ich operates on a sin gle 5V rail.
The bias is generated by the potential divider R216 and R217
this is 1.75V it is amplified by 1.43 by the opamp to give
approximately 2.5V at the output of the opamps IC202 and
IC203.
The diodes D200, D20 1, D202, D203 preven t over voltage
signals f r o m being presented to the inpu t of th e ADC, they do
not protec t the ADC i f one of the opamp fails, as th e diode wi ll
blow as well. The ADC itself is set t o op er ate as a m aster for t he
I2S interface and to have its internal high pass filter enabled.
Data is output from the ADC on pin 15, it also generates a bit
clock at 64xFS on pin 14 and a word clock at Fs on pin 13. The
master clock on pin 17 is an input and should be at 25 6xFs.
DAC
Refer to circuit diagram L896 Sheets 3,4,5,6
The DAC sheets are all essen tially th e same and so are on ly
described once below. The Sub DAC output has some minor
differences that are described in the text.
The DAC is a 24bit 192KHz part it consists of a serial interface
port, digital interpolation filter, multi bit sigma delta modulator
and stereo DAC. The DAC is in hardware configuration mode
(the control of emphasis and serial interface mode is set by
pulling pins high and low on the DAC). The serial interface is
set to I2S. The pins DM0 and DM1 control the de-emphasis
filters and are controlled via a serial to parallel latch (IC905)
con nect ed to the micro.
DA C re se t is use d to i ni tial is e the part and is u nder the con tr o l
of the microprocessor via a latch (IC905), it is an active low
signal. DAC MUTE on the same latch is an active low signal
and forces a s oft mute of th e output of the DAC.
The serial audio data interface consists of the DAC I2S LRCLK,
DAC I2S BCLK and DAC I2S DATA.
DAC I2S LRCLK is t he left right clock for th e au dio frames it
should be a square wave at the sampling frequency. The signal
is low during the left fram e and hi gh during the right frame.
DAC I2S BCLK is the bit clock for the data and data is clocked
int o the DAC on the r ising edge of this clock. The bit cloc k
operates a t 64 tim es the left right clock.
DAC I2S DAT A is th e actual audio data it is should be
present ed in I2S format that is one bit offset MS B first data of
up to 24bits. Each data frame consists of 32bits one offset bit 24
data bits and 7 empty zero bits. (If the actual data is less than 24
bits (i.e. from CD) the unused bits may also be empty zero.)
The output of the DAC is differential on the pin s 16 ,17 for left
and 12, 13 for right. This si gnal passes into a second ord er
multiple feedback type balanced to single ended filter. The filter
is a second order Bessel function with a three dB point of
app roximately 75KHz. This f ilter has been r ew orked on the
Bass output to have a three dB point of approximately 300Hz to
reduce the HF noise introduced by the bass management section.
The filter is unity gain however the balanced to single ended
conv ers ion intr oduces a gain of two. The output of the balanc ed
to single ended converter should be 2Vrms for a full scale input.
Following the filter is a buffer stage. The buffer stage performs
two fun ctions, it is a virtual earth mixer us ed to mix bass
in f o rmation into th e other channels when a sub woofer is not
pres ent. Switching the CMOS switch 74HCT4053 con trols the
mix. The cont rol of the CMOS switch is under microprocessor
control via a latch (IC904). The second function of the buffer i s
to p r ovide a ground sens e to the Au dio bo ard. Th is allows the
two boards to be loosely connected via a high impedance
with out introducing hu m. The differenc e between the grounds
on th e two PCBS is sens ed by the p osit ive input of the opamp
and added into the signal, this effectively removes any ground
vari ation bet ween the two PCBS. The full-s cale output of th e
DAC should produce 2v RMS at the output of the buffer stage.
DAC perfo rmance specific ation
THD better than -95dB (0.0018%)
Noise le vel at output of buffer bet ter than -100dB ref 2VRM S or
94dBV
Fre quency re s po nse +/- 0.4d B 10H z to 20KH z
The ot her co mponents on the cir cuit are decoup ling for the
DAC, OPAMP an d CMOS multiplexer. VMIDR and VMIDL
are t he output bias chai ns and s hould b e at approxima tely half
the Ana logue Voltage rail (2.5V). AVDDL and AVDDR are the
logic supply rails for the digital f ilter and the switched capacitor
filter.
DSP
Refer to circuit diagram L896 Sheet 7
Thi s is the Digital si gn al Proc essor sheet. IC701 is the main
DSP it decodes th e in coming data st ream to provide the 5
channels of discrete audio from Dolby Digital, DTS or M P EG
encoded material or a matrix decode of stereo information to 4
or five channel. The decoded data is passed to the second DSP
IC702 that performs post processing on the signal, performing
the THX equalisation Tone controls and Bas s management.