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Texas Instruments TMS320DM357 manual RX Mode Flow Chart

Models: TMS320DM357

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USB Controller Host and Peripheral Modes Operation

3.1.1.5.3RX Mode

In RX mode, all arriving data should be treated as part of a data phase until the expected amount of data has been received. If either a SETUP or an IN token is received while the endpoint is in RX state, a SetupEnd condition will occur as the controller expects only OUT tokens.

Three events can cause RX mode to be terminated before the expected amount of data has been received as shown in Figure 8:

1.The host sends an invalid token causing a SETUPEND condition (setting bit 4 of PERI_CSR0).

2.The host sends a packet which contains less than the maximum packet size for endpoint 0.

3.The host sends an empty data packet.

Until the transaction is terminated, the software unloads the FIFO when it receives an interrupt that indicates new data has arrived (setting RXPKTRDY bit of PERI_CSR0) and to clear RXPKTRDY by setting the SERV_RXPKTRDY bit of PERI_CSR0 (bit 6).

When the software detects the termination of a transfer (by receiving either the expected amount of data or an empty data packet), it should set the DATAEND bit (bit 3 of PERI_CSR0) to indicate to the controller that the data phase is complete and that the core should receive an acknowledge packet next.

Figure 8. RX Mode Flow Chart

RXmode

RxPktRdy No set

?

Yes

ReadCount0

register(n)

Unloadnbytes

fromFIFO

LastNo packet

?

Yes

Set

ServicedRxPktRdy

andDataEnd

state->IDLE

Return

Set

ServicedRxPktRdy

Return

SPRUGH3–November 2008

Universal Serial Bus (USB) Controller

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Texas Instruments TMS320DM357 manual RX Mode Flow Chart

Contents

Users Guide Submit Documentation Feedback Contents 100 Appendix a Type Register Host mode only HOSTTYPE0List of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Related Documentation From Texas Instruments Read This FirstNotational Conventions Notational Conventions Purpose of the Peripheral FeaturesFeatures Not Supported Cppi Functional Block DiagramExample 1. Initializing the USB Controller Supported Use Case ExamplesExample 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement Indexed and Non-Indexed Registers Signal DescriptionsUSB Pins Clock ControlDynamic Fifo Sizing USB PHY InitializationInterrupt Service Routine Flow Chart Peripheral Mode Control Transactions USB Controller Peripheral Mode OperationWrite Requests Zero Data RequestsRead Requests Endpoint 0 States CPU Actions at Transfer PhasesOUT Sequence of TransferEndpoint 0 Service Routine = Idle Service Endpoint 0 Flow ChartIdle Mode Flow Chart Idle ModeTX Mode Flow Chart TX ModeRX Mode Flow Chart RX ModeAdditional Conditions Error HandlingBulk Transactions Peripheral Mode Bulk In TransactionsSetup Bit Position Bit Field Name ConfigurationOperation Peripheral Mode Bulk OUT TransactionsDisnyet Interrupt Transactions Isochronous in Transactions Isochronous TransactionsIsochronous OUT Transactions Set to 1 to enable isochronous protocol Host Mode Control Transactions USB Controller Host Mode OperationSetup Phase of a Control Transaction Flow Chart Setup PhaseRxpktrdy Data PhaseOUT Data Phase Data Phase Flow ChartOUT Data Phase Flow Chart Completion of Setup or OUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data PhaseOUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions Cppi Transmit Buffer Descriptor DMA OperationDMA Transmit Operation Transmit BufferDescriptor. The software sets the Buffer Pointer Transmit Buffer Descriptor WordBits Name Description Bits Name Description 310 Buffer PointerEOQ Transmit DMA StateOperation Transmit QueueTransparent Mode and Rndis Mode Transmit DMA Operation DMA Receive Operation Rndis Mode SetupTransparent Mode Setup DMA Channel TearDownReceive Buffer Descriptor Word Cppi Receive Buffer DescriptorBit Field Receive DMA StateReceive Queue Rx Queue Flow ChartUSB Controller Host and Peripheral Modes Operation Receive Abort Handling Rndis Mode and Transparent Mode Receive DMA OperationUSB Interrupt Conditions DMA Teardown ProcedureInterrupt Handling Interrupts Generated by the USB ControllerUSB Interrupt Conditions DMA Interrupts Test ModesUSB Core Interrupts Testk TESTSE0NAKTestj Testpacket Forcehost Edma Event Support Reset ConsiderationsPower Management Interrupt SupportTransmit/Receive Cppi Channel 0 State Block Universal Serial Bus USB RegistersAcronym Register Description Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint Target Endpoint 4 Control Registers, Valid Only in Host Mode51Dh Bit Field Value Description Control Register CtrlrControl Register Ctrlr Field Descriptions Rndis Register Rndisr Field Descriptions Status Register StatrRndis Register Rndisr Status Register Statr Field DescriptionsAuto Request Register Autoreq Field Descriptions Auto Request Register AutoreqUSB USB Interrupt Source Register IntsrcrUSB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register IntsetrUSB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register IntclrrUSB Interrupt Mask Register Intmskr Field Descriptions USB Interrupt Mask Register IntmskrUSB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register IntmsksetrUSB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register IntmskclrrUSB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register IntmaskedrUSB Interrupt Vector Register Intvectr Field Descriptions USB End of Interrupt Register EoirUSB Interrupt Vector Register Intvectr USB End of Interrupt Register Eoir Field DescriptionsTransmit Cppi Teardown Register Tcppitdr Field Descriptions Transmit Cppi Control Register TcppicrTransmit Cppi Teardown Register Tcppitdr Transmit Cppi Control Register Tcppicr Field DescriptionsCppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register CppieoirComppending Transmit Cppi Masked Status Register TcppimsksrTransmit Cppi Raw Status Register Tcppirawsr Masked ComppendingComppendingintren Transmit Cppi Interrupt Enable Set Register TcppiiensetrTransmit Cppi Interrupt Enable Clear Register Tcppiienclrr Receive Cppi Control Register Rcppicr Field Descriptions RcppienableReceive Cppi Control Register Rcppicr Receive Cppi Masked Status Register RcppimsksrReceive Cppi Raw Status Register Rcppirawsr Receive Cppi Interrupt Enable Set Register RcppiensetrBufcnt Receive Cppi Interrupt Enable Clear Register RcppiienclrrReceive Buffer Count 0 Register RBUFCNT0 Receive Buffer Count 0 Register RBUFCNT0 Field DescriptionsReceive Buffer Count 2 Register RBUFCNT2 Field Descriptions Receive Buffer Count 1 Register RBUFCNT1Receive Buffer Count 2 Register RBUFCNT2 Receive Buffer Count 1 Register RBUFCNT1 Field DescriptionsTxqheadptr Receive Buffer Count 3 Register RBUFCNT3Transmit Cppi DMA State Word 0 TCPPIDMASTATEW0 Receive Buffer Count 3 Register RBUFCNT3 Field DescriptionsCurrdescriptorptr Truncatednoneop Transmit Cppi DMA State Word 1 TCPPIDMASTATEW1Transmit Cppi DMA State Word 2 TCPPIDMASTATEW2 SopdescriptorptrTransmit Cppi DMA State Word 4 TCPPIDMASTATEW4 Transmit Cppi DMA State Word 3 TCPPIDMASTATEW3Transmit Cppi Completion Pointer Tcppicompptr Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5Sopbufferoffset Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Rxqheadptr Receive Cppi DMA State Word 1 RCPPIDMASTATEW1Receive Cppi DMA State Word 3 RCPPIDMASTATEW3 Receive Cppi DMA State Word 2 RCPPIDMASTATEW2108 Pktlength Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Currbufferbytecnt Receive Cppi DMA State Word 6 RCPPIDMASTATEW6Receive Cppi Completion Pointer Rcppicompptr SopbufferbytecntFunction Address Register Faddr Power Management Register PowerPower Management Register Power Field Descriptions Readback / Compare ModeEP4TX Interrupt Register for Receive Endpoints 1 to 4 IntrrxField Descriptions EP4TX EP3TX EP2TX EP1TX EP0EP4RX Interrupt Enable Register for Intrtx IntrtxeInterrupt Enable Register for Intrrx Intrrxe EP4RX EP3RX EP2RX EP1RXInterrupt Enable Register for Intrrx Intrrxe Vbuserr Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendInterrupt Register for Common USB Interrupts Intrusb Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb IntrusbeEpsel Frame Number Register FrameFrame Number Register Frame Field Descriptions FramenumberForcehs Register to Enable the USB 2.0 Test Modes TestmodeForcehost ForcefsMaxpayload Servrxpktrdy ServsetupendSetupend FlushfifoDatatog DatatogwrenClrdatatog ISO Mode Dmaen Frcdatatog DmamodeControl Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Dmaen Disnyet Dmamode Datatogwren DataerrnaktimeoutControl Status Register for Host Receive Endpoint Hostrxcsr 127 Receive Count Register Rxcount Field Descriptions Count 0 Register COUNT0Receive Count Register Rxcount Count 0 Register COUNT0 Field DescriptionsSpeed Type Register Host mode only HOSTTYPE0Transmit Type Register Host mode only Hosttxtype Type Register Host mode only HOSTTYPE0 Field DescriptionsPolintvlnaklimit NAKLimit0 Register Host mode only HOSTNAKLIMIT0Transmit Interval Register Host mode only Hosttxinterval EP0NAKLIMITSpeed Prot Rendpn Receive Type Register Host mode only HostrxtypeReceive Interval Register Host mode only Hostrxinterval Mprxe Configuration Data Register ConfigdataConfiguration Data Register Configdata Field Descriptions 133 Data Transmit and Receive Fifo Register for Endpoint 0 FIFO0Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 1 FIFO1Transmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 4 FIFO4 Transmit and Receive Fifo Register for Endpoint 3 FIFO3Bdevice OTG Device Control Register DevctlOTG Device Control Register Devctl Field Descriptions Bdevice Fsdev Lsdev Vbus Hostmode Hostreq SessionReceive Endpoint Fifo Size Rxfifosz Field Descriptions Transmit Endpoint Fifo Size TxfifoszReceive Endpoint Fifo Size Rxfifosz Transmit Endpoint Fifo Size Txfifosz Field DescriptionsAddr Transmit Endpoint Fifo Address TxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Receive Endpoint Fifo Address Rxfifoaddr Field DescriptionsTransmit Hub Port Txhubport Transmit Function Address TxfuncaddrTransmit Hub Address Txhubaddr Receive Hub Port Rxhubport Receive Function Address RxfuncaddrReceive Hub Address Rxhubaddr 142 Additions/Modifications/Deletions Table A-1. Document Revision HistoryRfid Products ApplicationsDSP