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3.1.1.5.3RX Mode
In RX mode, all arriving data should be treated as part of a data phase until the expected amount of data has been received. If either a SETUP or an IN token is received while the endpoint is in RX state, a SetupEnd condition will occur as the controller expects only OUT tokens.
Three events can cause RX mode to be terminated before the expected amount of data has been received as shown in Figure 8:
1.The host sends an invalid token causing a SETUPEND condition (setting bit 4 of PERI_CSR0).
2.The host sends a packet which contains less than the maximum packet size for endpoint 0.
3.The host sends an empty data packet.
Until the transaction is terminated, the software unloads the FIFO when it receives an interrupt that indicates new data has arrived (setting RXPKTRDY bit of PERI_CSR0) and to clear RXPKTRDY by setting the SERV_RXPKTRDY bit of PERI_CSR0 (bit 6).
When the software detects the termination of a transfer (by receiving either the expected amount of data or an empty data packet), it should set the DATAEND bit (bit 3 of PERI_CSR0) to indicate to the controller that the data phase is complete and that the core should receive an acknowledge packet next.
Figure 8. RX Mode Flow Chart
RXmode
RxPktRdy No set
?
Yes
ReadCount0
register(n)
Unloadnbytes
fromFIFO
LastNo packet
?
Yes
Set
ServicedRxPktRdy
andDataEnd
Return
Set
ServicedRxPktRdy
Return
Universal Serial Bus (USB) Controller | 35 |