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3.3.2.4Receive Queue
Figure 15 shows an Rx Queue. Rx queue provide a logical queue of processor memory space for DMA packets to be received from DMA controller channel. Each channel has single Rx queue. There are no multiple queue as in transmit channels. Each queue has one associated Rx Queue Head Descriptor Pointer and one associated Rx Completion Pointer contained in the channel Rx DMA State. The Rx queue are linked lists of Rx buffer descriptors that constitute processor memory space for one or more packets to be received. Packet space is added to the tail of the list by the software and received packets are freed from the list by the DMA controller as each packet is received.
Figure 15. Rx Queue Flow Chart
SOP descriptor
Descriptor
Descriptor
Descriptor
EOP descriptor
Buffer
Buffer
Buffer
Buffer
Buffer
Rx queue head descriptor pointer
3.3.2.5Operation
∙After reset the software must write zeroes to all Rx DMA State registers (RCPPIDMASTATEW0, RCPPIDMASTATEW1, RCPPIDMASTATEW2, RCPPIDMASTATEW3, RCPPIDMASTATEW4, RCPPIDMASTATEW5 and RCPPIDMASTATEW6).
∙The software constructs receive queue in memory.
∙Enable DMA for the endpoint in the PERI_RXCSR or HOST_RXCSR by setting the DMAEN bit.
∙Enable the DMA ports by setting RCPPI_ENABLE bit of RCPPICR register.
∙Set the value in RBUFCNTn register (where n is the channel number) for the number of buffers available in the Rx queue. The hardware requires at least 3 available buffers to start the DMA. A new transfer will not be started if the buffer count is below 3. The value in RBUFCNTn decrements as DMA controller consumes the buffers for reception.
∙Write the head of the queue descriptor pointer to the RCPPIDMASTATEW1 register to start the DMA.
∙The USB controller will send IN token and wait for the data on the bus. Once data is received, DMA controller will transfer the data in the Rx queue from the endpoint FIFO. Once a complete DMA packet is received, interrupt associated with the DMA channel is asserted.
Universal Serial Bus (USB) Controller | 65 |
