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4.29 Receive Buffer Count 3 Register (RBUFCNT3)
The Receive Buffer Count 3 Register (RBUFCNT3) is shown in Figure 44 and described in Table 45.
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| Figure 44. Receive Buffer Count 3 Register (RBUFCNT3) | |
31 |
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| 16 |
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| Reserved |
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15 |
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| 0 |
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| BUFCNT |
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LEGEND: R/W = Read/Write; R = Read only; | |||
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| Table 45. Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions | |
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
BUFCNT | Receive CPPI Buffer Count 0 | ||
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| The current count of CPPI buffers in Receive channel 3 queue. Writes add to current value (not |
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| overwrite). The DMA requires a minimum of 3 RX buffers to operate. |
4.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)
The Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) is shown in Figure 45 and described in Table 46.
Figure 45. Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)
31 |
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| 16 |
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| TXQ_HEAD_PTR |
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15 |
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| 2 | 1 | 0 |
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| TXQ_HEAD_PTR | Reserved | IN_PACKET | |
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LEGEND: R/W = Read/Write; R = Read only; |
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| Table 46. Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions | ||||
Bit | Field | Value | Description |
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TXQ_HEAD_PTR | TX Queue Head Pointer |
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1 | Reserved | 0 | Reserved |
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0 | IN_PACKET |
| Flag indicating the DMA is in the middle of processing a packet |
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| 0 | Not currently in packet |
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| 1 | Currently in packet |
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Universal Serial Bus (USB) Controller | 101 | |
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