USB Controller Host and Peripheral Modes Operation | www.ti.com |
FIFO unload requests will probably be irregular. If the data sink for the endpoint is going to some external hardware, it may be better to minimize the requirement for additional buffering by waiting until the end of each frame before unloading the FIFO. This can be done by using the SOF_PULSE signal from the controller to trigger the unloading of the data packet. The SOF_PULSE is generated once per frame(/microframe). The interrupts may still be used to clear the RXPKTRDY bit in HOST_RXCSR.
3.2.4.1.3Error Handling
If a CRC or
3.2.4.2Host Mode: Isochronous Out Transactions
An Isochronous OUT transaction may be used to transfer periodic data from the host to the USB peripheral.
Following optional features are available for use with a Tx endpoint used in Host mode to transmit this data:
∙Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting transmission to the peripheral device. Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ register (bit 4).
∙DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO. This feature can be used to allow the DMA controller to load packets into the FIFO without processor intervention.
However, this feature is not particularly useful with isochronous endpoints because the packets transferred are often not maximum packet size.
When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set, endpoint interrupt will not be generated for completion of packet reception. Endpoint interrupt will be generated only in the error conditions.
3.2.4.2.1Setup
Before initiating any Isochronous OUT transactions:
∙The target function address needs to be set in the TXFUNCADDR register for the selected controller endpoint (TXFUNCADDR register is available for all endpoints from EP0 to EP4).
∙The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–Operating speed in the SPEED bit field (bits 7 and 6).
–Set 01 (binary value) in the PROT field for isochronous transfer.
–Endpoint Number of the target device in TENDPN field. This is the endpoint number contained in the OUT(Tx) endpoint descriptor returned by the target device during enumeration.
∙The TXMAXP register for the controller endpoint must be written with the maximum packet size (in bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint.
∙The HOST_TXINTERVAL register needs to be written with the required transaction interval (usually one transaction per frame/microframe).
∙The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for this endpoint).
∙The following bits of HOST_TXCSR register should be set as shown below:
–Set the MODE bit (bit 13) to 1 to ensure the FIFO is enabled (only necessary if the FIFO is shared with an Rx endpoint).
–Set the DMAEN bit ( bit 12) to 1 if a DMA request is required for this endpoint.
–The FRCDATATOG bit (bit 12) is ignored for isochronous transactions.
–Set the DMAMODE bit (bit 10) to 1 when DMA is enabled and the endpoint interrupt is not needed for each packet transmission.
56 | Universal Serial Bus (USB) Controller |
