www.ti.com

Registers

4.2Status Register (STATR)

The Status Register (STATR) is shown in Figure 17 and described in Table 18.

Figure 17. Status Register (STATR)

31

 

 

 

16

 

 

 

Reserved

 

 

 

 

R-0

 

15

 

 

1

0

 

 

 

Reserved

DRVVBUS

 

 

 

R-0

R-0

LEGEND: R = Read only; -n= value after reset

 

 

 

 

Table 18. Status Register (STATR) Field Descriptions

 

Bit

Field

Value

Description

 

31-1

Reserved

0

Reserved

 

0

DRVVBUS

 

Current DRVVBUS value.

 

 

 

0

DRVVBUS value is logic 0

 

 

 

1

DRVVBUS value is logic 1

 

4.3RNDIS Register (RNDISR)

The RNDIS Register (RNDISR) is shown in Figure 18 and described in Table 19.

Figure 18. RNDIS Register (RNDISR)

31

20

19

18

17

16

Reserved

 

RX4EN

RX3EN

RX2EN

RX1EN

R-0

 

R/W-0

R/W-0

R/W-0

R/W-0

15

4

3

2

1

0

Reserved

 

TX4EN

TX3EN

TX2EN

TX1EN

R-0

 

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

 

 

 

 

 

Table 19. RNDIS Register (RNDISR) Field Descriptions

 

Bit

Field

Value

Description

 

31-20

Reserved

0

Reserved

 

19

RX4EN

0-1

Receive Endpoint 4 RNDIS mode enable.

 

18

RX3EN

0-1

Receive Endpoint 3 RNDIS mode enable.

 

17

RX2EN

0-1

Receive Endpoint 2 RNDIS mode enable.

 

16

RX1EN

0-1

Receive Endpoint 1 RNDIS mode enable.

 

15-4

Reserved

0

Reserved

 

3

TX4EN

0-1

Transmit Endpoint 4 RNDIS mode enable.

 

2

TX3EN

0-1

Transmit Endpoint 3 RNDIS mode enable.

 

1

TX2EN

0-1

Transmit Endpoint 2 RNDIS mode enable.

 

0

TX1EN

0-1

Transmit Endpoint 1 RNDIS mode enable.

 

SPRUGH3–November 2008

Universal Serial Bus (USB) Controller

83

Submit Documentation Feedback

 

 

Page 83
Image 83
Texas Instruments TMS320DM357 manual Rndis Register Rndisr, Status Register Statr Field Descriptions