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4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR)
The Transmit CPPI Masked Status Register (TCPPIMSKSR) is shown in Figure 32 and described in Table 33.
Figure 32. Transmit CPPI Masked Status Register (TCPPIMSKSR)
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| 16 |
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| Reserved |
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15 |
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| 4 | 3 | 0 |
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| Reserved | MASKED COMP_PENDING | ||
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LEGEND: R = Read only; |
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| Table 33. Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions |
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Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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MASKED COMP_PENDING | Masked High Priority Transmit Completion Pending |
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| Indicators for channels 3 to 0 Raw Transmit high priority completion indicators bitwise | ||
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| anded with Transmit high priority completion mask bits |
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4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR)
The Transmit CPPI Raw Status Register (TCPPIRAWSR) is shown in Figure 33 and described in Table 34.
Figure 33. Transmit CPPI Raw Status Register (TCPPIRAWSR)
31 |
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| 16 |
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| Reserved |
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15 |
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| 4 | 3 | 0 |
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| Reserved |
| COMP_PENDING |
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LEGEND: R = Read only; |
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| Table 34. Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions | ||||
Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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COMP_PENDING | Raw High Priority Transmit Completion Pending |
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| Indicators for channels 3 to 0 Active high flags which indicate that a packet has completed | ||
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| transmission on the high priority queue |
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Universal Serial Bus (USB) Controller | 95 | |
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