Texas Instruments TMS320DM357 specs

Registers

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4.23 Receive CPPI Raw Status Register (RCPPIRAWSR)

The Receive CPPI Raw Status Register (RCPPIRAWSR) is shown in Figure 38 and described in Table 39.

Figure 38. Receive CPPI Raw Status Register (RCPPIRAWSR)

31					16
			Reserved
			R-0
15			4	3	0
			Reserved		COMP_PENDING
			R-0		R-0
LEGEND: R = Read only; -n= value after reset
	Table 39. Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions
Bit	Field	Value	Description
31-4	Reserved	0	Reserved
3-0	COMP_PENDING	0-Fh	Raw Receive Completion Pending
			Indicators for channels 3 to 0 Active high flags which indicate that a packet has completed
			reception

4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)

The Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) is shown in Figure 39 and described in Table 40.

Figure 39. Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)

31					16
			Reserved
			R-0
15			4	3	0
		Reserved		COMP_PENDING_INTR_EN
			R-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Table 40. Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions
Bit	Field	Value	Description
31-4	Reserved	0	Reserved
3-0	COMP_PENDING_INTR_EN	0-Fh	Receive CPPI Interrupt Enables
			These are active high interrupt enables corresponding to the Receive CPPI Completion
			Pending status bits. Writing a 1 to any of the bits in the Receive CPPI Interrupt Enable
			Set Register will result in setting of the corresponding bit in the Receive CPPI Interrupt
			Enable Register.

98

Universal Serial Bus (USB) Controller

SPRUGH3–November 2008

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Texas Instruments TMS320DM357 manual Receive Cppi Raw Status Register Rcppirawsr

Contents

Users Guide Submit Documentation Feedback Contents 100 Type Register Host mode only HOSTTYPE0 Appendix a List of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Read This First Related Documentation From Texas Instruments Notational Conventions Notational Conventions Purpose of the Peripheral FeaturesFeatures Not Supported Functional Block Diagram Cppi Supported Use Case Examples Example 1. Initializing the USB Controller Example 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement Clock Control Signal DescriptionsUSB Pins Indexed and Non-Indexed Registers USB PHY Initialization Dynamic Fifo Sizing Interrupt Service Routine Flow Chart USB Controller Peripheral Mode Operation Peripheral Mode Control Transactions Zero Data Requests Write Requests Read Requests CPU Actions at Transfer Phases Endpoint 0 States Sequence of Transfer OUT Endpoint 0 Service Routine Service Endpoint 0 Flow Chart = Idle Idle Mode Idle Mode Flow Chart TX Mode TX Mode Flow Chart RX Mode RX Mode Flow Chart Error Handling Additional Conditions Bit Position Bit Field Name Configuration Peripheral Mode Bulk In TransactionsSetup Bulk Transactions Peripheral Mode Bulk OUT Transactions Operation Disnyet Interrupt Transactions Isochronous Transactions Isochronous in Transactions Isochronous OUT Transactions Set to 1 to enable isochronous protocol USB Controller Host Mode Operation Host Mode Control Transactions Setup Phase Setup Phase of a Control Transaction Flow Chart Data Phase Rxpktrdy Data Phase Flow Chart OUT Data Phase OUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data Phase Completion of Setup or OUT Data Phase Flow Chart OUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions Transmit Buffer DMA OperationDMA Transmit Operation Cppi Transmit Buffer Descriptor Bits Name Description 310 Buffer Pointer Transmit Buffer Descriptor WordBits Name Description Descriptor. The software sets the Buffer Pointer Transmit DMA State EOQ Transmit Queue Operation Transparent Mode and Rndis Mode Transmit DMA Operation DMA Channel TearDown Rndis Mode SetupTransparent Mode Setup DMA Receive Operation Cppi Receive Buffer Descriptor Receive Buffer Descriptor Word Receive DMA State Bit Field Rx Queue Flow Chart Receive Queue USB Controller Host and Peripheral Modes Operation Rndis Mode and Transparent Mode Receive DMA Operation Receive Abort Handling Interrupts Generated by the USB Controller DMA Teardown ProcedureInterrupt Handling USB Interrupt Conditions USB Interrupt Conditions DMA Interrupts Test ModesUSB Core Interrupts Testk TESTSE0NAKTestj Testpacket Forcehost Interrupt Support Reset ConsiderationsPower Management Edma Event Support Transmit/Receive Cppi Channel 0 State Block Universal Serial Bus USB RegistersAcronym Register Description Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Target Endpoint 4 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint 51Dh Bit Field Value Description Control Register CtrlrControl Register Ctrlr Field Descriptions Status Register Statr Field Descriptions Status Register StatrRndis Register Rndisr Rndis Register Rndisr Field Descriptions Auto Request Register Autoreq Auto Request Register Autoreq Field Descriptions USB USB Interrupt Source Register IntsrcrUSB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register Intsetr USB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register Intclrr USB Interrupt Mask Register Intmskr USB Interrupt Mask Register Intmskr Field Descriptions USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register Intmaskedr USB End of Interrupt Register Eoir Field Descriptions USB End of Interrupt Register EoirUSB Interrupt Vector Register Intvectr USB Interrupt Vector Register Intvectr Field Descriptions Transmit Cppi Control Register Tcppicr Field Descriptions Transmit Cppi Control Register TcppicrTransmit Cppi Teardown Register Tcppitdr Transmit Cppi Teardown Register Tcppitdr Field Descriptions Cppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register Cppieoir Masked Comppending Transmit Cppi Masked Status Register TcppimsksrTransmit Cppi Raw Status Register Tcppirawsr Comppending Comppendingintren Transmit Cppi Interrupt Enable Set Register TcppiiensetrTransmit Cppi Interrupt Enable Clear Register Tcppiienclrr Receive Cppi Masked Status Register Rcppimsksr RcppienableReceive Cppi Control Register Rcppicr Receive Cppi Control Register Rcppicr Field Descriptions Receive Cppi Interrupt Enable Set Register Rcppiensetr Receive Cppi Raw Status Register Rcppirawsr Receive Buffer Count 0 Register RBUFCNT0 Field Descriptions Receive Cppi Interrupt Enable Clear Register RcppiienclrrReceive Buffer Count 0 Register RBUFCNT0 Bufcnt Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Receive Buffer Count 1 Register RBUFCNT1Receive Buffer Count 2 Register RBUFCNT2 Receive Buffer Count 2 Register RBUFCNT2 Field Descriptions Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions Receive Buffer Count 3 Register RBUFCNT3Transmit Cppi DMA State Word 0 TCPPIDMASTATEW0 Txqheadptr Sopdescriptorptr Transmit Cppi DMA State Word 1 TCPPIDMASTATEW1Transmit Cppi DMA State Word 2 TCPPIDMASTATEW2 Currdescriptorptr Truncatednoneop Transmit Cppi DMA State Word 3 TCPPIDMASTATEW3 Transmit Cppi DMA State Word 4 TCPPIDMASTATEW4 Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5 Transmit Cppi Completion Pointer Tcppicompptr Sopbufferoffset Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Rxqheadptr Receive Cppi DMA State Word 2 RCPPIDMASTATEW2 Receive Cppi DMA State Word 3 RCPPIDMASTATEW3 108 Pktlength Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Sopbufferbytecnt Receive Cppi DMA State Word 6 RCPPIDMASTATEW6Receive Cppi Completion Pointer Rcppicompptr Currbufferbytecnt Readback / Compare Mode Power Management Register PowerPower Management Register Power Field Descriptions Function Address Register Faddr EP4TX EP3TX EP2TX EP1TX EP0 Interrupt Register for Receive Endpoints 1 to 4 IntrrxField Descriptions EP4TX EP4RX EP3RX EP2RX EP1RX Interrupt Enable Register for Intrtx IntrtxeInterrupt Enable Register for Intrrx Intrrxe EP4RX Interrupt Enable Register for Intrrx Intrrxe Vbuserr Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendInterrupt Register for Common USB Interrupts Intrusb Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb Intrusbe Framenumber Frame Number Register FrameFrame Number Register Frame Field Descriptions Epsel Forcefs Register to Enable the USB 2.0 Test Modes TestmodeForcehost Forcehs Maxpayload Flushfifo ServsetupendSetupend Servrxpktrdy Datatogwren Datatog ISO Mode Dmaen Frcdatatog Dmamode Clrdatatog Control Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Dmaen Disnyet Dmamode Datatogwren DataerrnaktimeoutControl Status Register for Host Receive Endpoint Hostrxcsr 127 Count 0 Register COUNT0 Field Descriptions Count 0 Register COUNT0Receive Count Register Rxcount Receive Count Register Rxcount Field Descriptions Type Register Host mode only HOSTTYPE0 Field Descriptions Type Register Host mode only HOSTTYPE0Transmit Type Register Host mode only Hosttxtype Speed EP0NAKLIMIT NAKLimit0 Register Host mode only HOSTNAKLIMIT0Transmit Interval Register Host mode only Hosttxinterval Polintvlnaklimit Speed Prot Rendpn Receive Type Register Host mode only HostrxtypeReceive Interval Register Host mode only Hostrxinterval Mprxe Configuration Data Register ConfigdataConfiguration Data Register Configdata Field Descriptions 133 Transmit and Receive Fifo Register for Endpoint 0 FIFO0 Data Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 1 FIFO1Transmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 3 FIFO3 Transmit and Receive Fifo Register for Endpoint 4 FIFO4 Bdevice Fsdev Lsdev Vbus Hostmode Hostreq Session OTG Device Control Register DevctlOTG Device Control Register Devctl Field Descriptions Bdevice Transmit Endpoint Fifo Size Txfifosz Field Descriptions Transmit Endpoint Fifo Size TxfifoszReceive Endpoint Fifo Size Rxfifosz Receive Endpoint Fifo Size Rxfifosz Field Descriptions Receive Endpoint Fifo Address Rxfifoaddr Field Descriptions Transmit Endpoint Fifo Address TxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Addr Transmit Hub Port Txhubport Transmit Function Address TxfuncaddrTransmit Hub Address Txhubaddr Receive Hub Port Rxhubport Receive Function Address RxfuncaddrReceive Hub Address Rxhubaddr 142 Table A-1. Document Revision History Additions/Modifications/Deletions Rfid Products ApplicationsDSP