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Registers | www.ti.com |
4.23 Receive CPPI Raw Status Register (RCPPIRAWSR)
The Receive CPPI Raw Status Register (RCPPIRAWSR) is shown in Figure 38 and described in Table 39.
Figure 38. Receive CPPI Raw Status Register (RCPPIRAWSR)
31 |
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| 16 |
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| Reserved |
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15 |
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| 4 | 3 | 0 |
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| Reserved |
| COMP_PENDING |
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LEGEND: R = Read only; |
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| Table 39. Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions | ||||
Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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COMP_PENDING | Raw Receive Completion Pending |
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| Indicators for channels 3 to 0 Active high flags which indicate that a packet has completed | ||
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| reception |
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4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)
The Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) is shown in Figure 39 and described in Table 40.
Figure 39. Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)
31 |
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| 16 |
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| Reserved |
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15 |
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| 4 | 3 | 0 |
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| Reserved | COMP_PENDING_INTR_EN | ||
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LEGEND: R/W = Read/Write; R = Read only; |
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| Table 40. Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions |
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Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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COMP_PENDING_INTR_EN | Receive CPPI Interrupt Enables |
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| These are active high interrupt enables corresponding to the Receive CPPI Completion | ||
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| Pending status bits. Writing a 1 to any of the bits in the Receive CPPI Interrupt Enable | ||
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| Set Register will result in setting of the corresponding bit in the Receive CPPI Interrupt | ||
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| Enable Register. |
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98 | Universal Serial Bus (USB) Controller |