Texas Instruments TMS320DM357 Receive Cppi DMA State Word 0 RCPPIDMASTATEW0, Sopbufferoffset

www.ti.com			Registers
	Table 52. Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions
Bit	Field	Value	Description
31-2	DESC_ADDR	0-3FFF FFFFh	Descriptor Address
			This field contains the 30-bit word aligned pointer of the end of packet descriptor that the
			DMA has last processed
1	Reserved	0	Reserved
0	WRBK_MODE		Writeback/Compare Mode. This bit controls the action that is to be taken when this location
			is written.

0Compare Mode. Indicates that the value that is presented on bits 31:2 of the write data should be compared against the value that is currently contained in bits 31:2 of this location. If the two match, the interrupt bit corresponding to this Tx Queue should be deasserted.

1Writeback Mode. Indicates that the value that is presented on bits 31:2 of the write data should be written to this location and the interrupt for this Tx Queue should be asserted. This bit is read as zero.

4.37Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)

The Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) is shown in Figure 52 and described in Table 53.

Figure 52. Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)

31					16
			Reserved
			R-0
15			8	7	0
	Reserved			SOP_BUFFER_OFFSET
	R/W-0			R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Table 53. Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions
Bit	Field	Value	Description
31-8	Reserved	0-7FFF FFh	Reserved
7-0	SOP_BUFFER_OFFSET	0-FFh	Start of Packet Buffer Offset
			Controls how many bytes the Receive DMA will skip at the beginning of the start
			of packet buffer before beginning to fill the buffer with receive data. This field is
			programmed by the Host software when the channel is set up to facilitate
			addition of various protocol encapsulation headers for retransmission of received
			packets.

4.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)

The Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) is shown in Figure 53 and described in Table 54.

SPRUGH3–November 2008 Universal Serial Bus (USB) Controller 105

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