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Registers | www.ti.com |
4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR)
The Control Status Register for Host Receive Endpoint (HOST_RXCSR) is shown in Figure 78 and described in Table 79.
Figure 78. Control Status Register for Host Receive Endpoint (HOST_RXCSR)
| 15 | 14 |
| 13 | 12 | 11 |
| 10 | 9 | 8 |
| Reserved | DMAEN | DISNYET | DMAMODE | DATATOGWREN | DATATOG | Reserved | |||
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| 7 | 6 |
| 5 | 4 | 3 |
| 2 | 1 | 0 |
CLRDATATOG | RXSTALL | REQPKT | FLUSHFIFO | DATAERR_NAK | ERROR | FIFOFULL | RXPKTRDY | |||
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| TIMEOUT |
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LEGEND: R/W = Read/Write; R = Read only; W = Write only; |
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| Table 79. Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions | |||||||||
Bit | Field |
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| Value | Description |
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Reserved |
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| 0 | Reserved |
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13 | DMAEN |
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| Set this bit to enable the DMA request for the Receive endpoints. |
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12 | DISNYET |
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| Set this bit to disable the sending of NYET handshakes. When set, all successfully received | ||||||
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| Receive packets are ACKED including at the point at which the FIFO becomes full. | |||||
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| Note: This bit only has any effect in | |||||
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| Interrupt endpoints. |
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11 | DMAMODE |
| 0 | This bit should always be cleared to 0. |
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10 | DATATOGWREN |
| Set this bit to enable the DATATOG bit to be written. This bit is automatically cleared once | |||||||
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| the new value is written to DATATOG. |
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9 | DATATOG |
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| When read, this bit indicates the current state of the Receive EP data toggle. If | ||||||
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| DATATOGWREN is high, this bit can be written with the required setting of the data toggle. | |||||
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| If DATATOGWREN is low, any value written to this bit is ignored. |
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8 | Reserved |
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| 0 | Reserved |
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7 | CLRDATATOG |
| Set this bit to reset the endpoint data toggle to 0. |
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6 | RXSTALL |
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| When a STALL handshake is received, this bit is set and an interrupt is generated. You | ||||||
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| should clear this bit. |
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5 | REQPKT |
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| Set this bit to request an IN transaction. It is cleared when RXPKTRDY is set. | ||||||
4 | FLUSHFIFO |
| Set this bit to flush the next packet to be read from the endpoint Receive FIFO. The FIFO | |||||||
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| pointer is reset and the RXPKTRDY bit is cleared. |
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| Note: FLUSHFIFO has no effect unless RXPKTRDY is set. Also note that, if the FIFO is | |||||
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3 | DATAERR_NAKTIMEOUT | When operating in ISO mode, this bit is set when RXPKTRDY is set if the data packet has | ||||||||
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| a CRC or | |||||
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| be set when the Receive endpoint is halted following the receipt of NAK responses for | |||||
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| longer than the time set as the NAK Limit by the RXINTERVAL register. You should clear | |||||
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| this bit to allow the endpoint to continue. |
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2 | ERROR |
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| The USB controller sets this bit when 3 attempts have been made to receive a packet and | ||||||
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| no data packet has been received. You should clear this bit. An interrupt is generated when | |||||
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| the bit is set. |
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| Note: This bit is only valid when the transmit endpoint is operating in Bulk or Interrupt | |||||
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| mode. In ISO mode, it always returns zero. |
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1 | FIFOFULL |
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| This bit is set when no more packets can be loaded into the Receive FIFO. |
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0 | RXPKTRDY |
| This bit is set when a data packet has been received. You should clear this bit when the | |||||||
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| packet has been unloaded from the Receive FIFO. An interrupt is generated when the bit is | |||||
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| set. |
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126 | Universal Serial Bus (USB) Controller |