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4.21 Receive CPPI Control Register (RCPPICR)
The Receive CPPI Control Register (RCPPICR) is shown in Figure 36 and described in Table 37.
Figure 36. Receive CPPI Control Register (RCPPICR)
31 |
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| 16 |
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| Reserved |
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15 |
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| 1 | 0 |
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| Reserved | RCPPI_ENABLE |
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LEGEND: R/W = Read/Write; R = Read only; |
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| Table 37. Receive CPPI Control Register (RCPPICR) Field Descriptions |
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Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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0 | RCPPI_ENABLE | Receive CPPI Enable Controls if the Receive CPPI DMA controller is enabled. Be sure to program | ||
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| the CPPI chain and set the DMA state words before enabling the DMA. Failure to initialize the DMA | |
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| before enabling could result in spurious transfers and memory corruption. |
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| 0 | Receive CPPI DMA is disabled. |
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| 1 | Receive CPPI DMA is enabled. |
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4.22 Receive CPPI Masked Status Register (RCPPIMSKSR)
The Receive CPPI Masked Status Register (RCPPIMSKSR) is shown in Figure 37 and described in Table 38.
Figure 37. Receive CPPI Masked Status Register (RCPPIMSKSR)
31 |
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| 16 |
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| Reserved |
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15 |
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| 4 | 3 | 0 |
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| Reserved | MASKED_COMP_PENDING | ||
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LEGEND: R = Read only; |
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| Table 38. Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions |
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Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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MASKED_COMP_PENDING | Masked Receive Completion Pending |
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| Indicators for channels 3 to 0 Raw Receive completion indicators bitwise ANDed with | ||
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| Receive completion mask bits |
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Universal Serial Bus (USB) Controller | 97 | |
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