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4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
The Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) is shown in Figure 91 and described in Table 92.
Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
31 | 0 |
DATA
LEGEND: R/W = Read/Write;
Table 92. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions
Bit | Field | Value | Description |
DATA |
| Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint. | |
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| Reading from these addresses unloads data from the Receive FIFO for the corresponding |
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| endpoint. |
4.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
The Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) is shown in Figure 92 and described in Table 93.
Figure 92. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
31 | 0 |
DATA
LEGEND: R/W = Read/Write;
Table 93. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions
Bit | Field | Value | Description |
DATA |
| Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint. | |
|
|
| Reading from these addresses unloads data from the Receive FIFO for the corresponding |
|
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| endpoint. |
136 | Universal Serial Bus (USB) Controller | |
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