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4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
The Control Status Register for Host Transmit Endpoint (HOST_TXCSR) is shown in Figure 75 and described in Table 76.
Figure 75. Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
15 | 14 | 13 |
| 12 | 11 | 10 | 9 | 8 |
Reserved | MODE | DMAEN | FRCDATATOG | DMAMODE | DATATOGWREN | DATATOG | ||
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7 | 6 |
| 5 | 4 | 3 | 2 | 1 | 0 |
NAK_TIMEOUT | CLRDATATOG | RXSTALL | SETUPPKT FLUSHFIFO | ERROR | FIFONOTEMPTY | TXPKTRDY | ||
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LEGEND: R/W = Read/Write; R = Read only; W = Write only;
Table 76. Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
13 | MODE | Set this bit to enable the endpoint direction as Tx, and clear this bit to enable it as Rx. | |
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| Note: This bit has any effect only where the same endpoint FIFO is used for both Transmit and |
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| Receive transactions. |
12 | DMAEN | Set this bit to enable the DMA request for the Tx endpoint. | |
11 | FRCDATATOG | Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the | |
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| FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints that |
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| are used to communicate rate feedback for Isochronous endpoints. |
10 | DMAMODE | When using DMA, clear this bit to receive an interrupt for each packet, or set this bit to only receive | |
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| error interrupts. |
9 | DATATOGWREN | Set this bit to enable the DATATOG bit to be written. This bit is automatically cleared once the new | |
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| value is written to DATATOG. |
8 | DATATOG | When read, this bit indicates the current state of the Tx EP data toggle. If DATATOGWREN is high, | |
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| this bit can be written with the required setting of the data toggle. If DATATOGWREN is low, any |
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| value written to this bit is ignored. |
7 | NAK_TIMEOUT | This bit will be set when the Tx endpoint is halted following the receipt of NAK responses for longer | |
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| than the time set as the NAKLIMIT by the TXINTERVAL register. It should be cleared to allow the |
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| endpoint to continue. |
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| Note: This is valid only for Bulk endpoints. |
6 | CLRDATATOG | Set this bit to reset the endpoint data toggle to 0. | |
5 | RXSTALL | This bit is set when a STALL handshake is received. The FIFO is flushed and the TXPKTRDY bit is | |
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| cleared. You should clear this bit. |
4 | SETUPPKT | Set this bit at the same time as TXPKTRDY is set, to send a SETUP token instead of an OUT | |
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| token for the transaction. |
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| Note: Setting this bit also clears the DATATOG bit. |
3 | FLUSHFIFO | Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer | |
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| is reset and the TXPKTRDY bit is cleared. |
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| Note: FlushFIFO has no effect unless TXPKTRDY is set. Also note that, if the FIFO is |
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2 | ERROR | The USB controller sets this bit when 3 attempts have been made to send a packet and no | |
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| handshake packet has been received. You should clear this bit. An interrupt is generated when the |
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| bit is set. This is valid only when the endpoint is operating in Bulk or Interrupt mode. |
1 | FIFONOTEMPTY | The USB controller sets this bit when there is at least 1 packet in the Tx FIFO. | |
0 | TXPKTRDY | Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet | |
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| has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. |
Universal Serial Bus (USB) Controller | 123 | |
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