Texas Instruments TMS320DM357 manual Control Status Register for Host Transmit Endpoint Hosttxcsr

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4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR)

The Control Status Register for Host Transmit Endpoint (HOST_TXCSR) is shown in Figure 75 and described in Table 76.

Figure 75. Control Status Register for Host Transmit Endpoint (HOST_TXCSR)

15	14	13		12	11	10	9	8
Reserved	MODE		DMAEN		FRCDATATOG	DMAMODE	DATATOGWREN	DATATOG
R-0	R/W-0			R/W-0	R/W-0	R/W-0	W-0	R/W-0
7	6		5	4	3	2	1	0
NAK_TIMEOUT	CLRDATATOG	RXSTALL		SETUPPKT FLUSHFIFO		ERROR	FIFONOTEMPTY	TXPKTRDY
R/W-0	W-0		R/W-0	R/W-0	W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n= value after reset

Table 76. Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions

Bit	Field	Value	Description
15-14	Reserved	0	Reserved
13	MODE	0-1	Set this bit to enable the endpoint direction as Tx, and clear this bit to enable it as Rx.
			Note: This bit has any effect only where the same endpoint FIFO is used for both Transmit and
			Receive transactions.
12	DMAEN	0-1	Set this bit to enable the DMA request for the Tx endpoint.
11	FRCDATATOG	0-1	Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the
			FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints that
			are used to communicate rate feedback for Isochronous endpoints.
10	DMAMODE	0-1	When using DMA, clear this bit to receive an interrupt for each packet, or set this bit to only receive
			error interrupts.
9	DATATOGWREN	0-1	Set this bit to enable the DATATOG bit to be written. This bit is automatically cleared once the new
			value is written to DATATOG.
8	DATATOG	0-1	When read, this bit indicates the current state of the Tx EP data toggle. If DATATOGWREN is high,
			this bit can be written with the required setting of the data toggle. If DATATOGWREN is low, any
			value written to this bit is ignored.
7	NAK_TIMEOUT	0-1	This bit will be set when the Tx endpoint is halted following the receipt of NAK responses for longer
			than the time set as the NAKLIMIT by the TXINTERVAL register. It should be cleared to allow the
			endpoint to continue.
			Note: This is valid only for Bulk endpoints.
6	CLRDATATOG	0-1	Set this bit to reset the endpoint data toggle to 0.
5	RXSTALL	0-1	This bit is set when a STALL handshake is received. The FIFO is flushed and the TXPKTRDY bit is
			cleared. You should clear this bit.
4	SETUPPKT	0-1	Set this bit at the same time as TXPKTRDY is set, to send a SETUP token instead of an OUT
			token for the transaction.
			Note: Setting this bit also clears the DATATOG bit.
3	FLUSHFIFO	0-1	Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer
			is reset and the TXPKTRDY bit is cleared.
			Note: FlushFIFO has no effect unless TXPKTRDY is set. Also note that, if the FIFO is
			double-buffered, FLUSHFIFO may need to be set twice to completely clear the FIFO.
2	ERROR	0-1	The USB controller sets this bit when 3 attempts have been made to send a packet and no
			handshake packet has been received. You should clear this bit. An interrupt is generated when the
			bit is set. This is valid only when the endpoint is operating in Bulk or Interrupt mode.
1	FIFONOTEMPTY	0-1	The USB controller sets this bit when there is at least 1 packet in the Tx FIFO.
0	TXPKTRDY	0-1	Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet
			has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.

SPRUGH3–November 2008	Universal Serial Bus (USB) Controller	123
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