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3.2.4Isochronous Transactions
3.2.4.1Host Mode: Isochronous IN Transactions
An Isochronous IN transaction is used to transfer periodic data from the USB peripheral to the host.
The following optional features are available for use with an Rx endpoint used in Host mode to receive this data:
∙Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception from the host. This allows that one packet can be received while another is being read. Double packet buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
∙DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention. However, this feature is not particularly useful with isochronous endpoints because the packets transferred are often not maximum packet size.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception. Endpoint interrupt will be generated only in the error conditions.
∙AutoRequest: When the AutoRequest feature is enabled, the REQPKT bit of HOST_RXCSR (bit 5) will be automatically set when the RXPKTRDY bit is cleared.
This feature is applicable only when DMA is enabled. To enable AutoRequest feature, set the AUTOREQ register for the DMA channel associated for the endpoint.
3.2.4.1.1Setup
Before initiating an Isochronous IN Transactions in Host mode:
∙The target function address needs to be set in the RXFUNCADDR register for the selected controller endpoint (RXFUNCADDR register is available for all endpoints from EP0 to EP4).
∙The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–Operating speed in the SPEED bit field (bits 7 and 6).
–Set 01 (binary value) in the PROT field for isochronous transfer.
–Endpoint Number of the target device in RENDPN field. This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration.
∙The RXMAXP register for the controller endpoint must be written with the maximum packet size (in bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint.
∙The HOST_RXINTERVAL register needs to be written with the required transaction interval (usually one transaction per frame/microframe).
∙The relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for this endpoint).
∙The following bits of HOST_RXCSR register should be set as shown below:
–Set the DMAEN bit ( bit 13) to 1 if a DMA request is required for this endpoint.
–Clear the DISNYET it (bit 12) to 0 to allow normal PING flow control. This will only affect High Speed transactions.
–Always clear the DMAMODE bit (bit 11) to 0.
∙If DMA is enabled, AUTOREQ register can be set for generating IN tokens automatically after receiving the data. Set the bit field RXn_AUTOREQ (where n is the endpoint number) with binary value 01 or 11.
3.2.4.1.2Operation
The operation starts with the software setting REQPKT bit of HOST_RXCSR (bit 5). This causes the controller to send an IN token to the target.
When a packet is received, an interrupt is generated which the software may use to unload the packet from the FIFO and clear the RXPKTRDY bit in the HOST_RXCSR register (bit 0) in the same way as for a Bulk Rx endpoint. As the interrupt could occur almost any time within a frame(/microframe), the timing of
Universal Serial Bus (USB) Controller | 55 |
