Texas Instruments TMS320DM357 guide

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USB Controller Host and Peripheral Modes Operation

3.2.1.4IN Status Phase (following SETUP Phase or OUT Data Phase)

For the IN Status Phase of a Control Transaction (Figure 12), the software driving the USB Host device needs to:

1.Set the STATUSPKT and REQPKT bits of HOST_CSR0 (bit 6 and bit 5, respectively).

2.Wait while the controller sends an IN token and receives a response from the USB peripheral device.

Figure 12. Completion of SETUP or OUT Data Phase Flow Chart

Completion of either SETUP phase or OUT data phase

		No			NAK limit
		No			reached
					reached
					?

	Error count
	Error count
	cleared					Yes

NAK Timeout set

Endpoint halted

Interrupt generated

ReqPkt

and StatusPkt

both set

?

Yes

IN token sent

STALL received

?

No

Yes NAK received

?

No

Data1 received

?

No

Error count incremented

No Error count=3

?

	No
		RxStall set		Command could
	Yes	RxStall set		not be completed
		ReqPkt cleared		not be completed
		ReqPkt cleared
		Error Count cleared
		Interrupt generated
	Yes	ACK sent	ReqPkt cleared
	Yes	RxPktRdy	Error Count cleared
		RxPktRdy	Error Count cleared
		set	Interrupt generated
			Transaction
				complete
				Implies problem
		Error bit set		at peripheral end
	Yes	Error bit set		of connection.
		ReqPkt cleared		of connection.
		ReqPkt cleared
		Error Count cleared
		Interrupt generated
				Transaction deemed
				complete

SPRUGH3–November 2008

Universal Serial Bus (USB) Controller

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Texas Instruments TMS320DM357 manual Status Phase following Setup Phase or OUT Data Phase

Contents

Users Guide Submit Documentation Feedback Contents 100 Appendix a Type Register Host mode only HOSTTYPE0 List of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Related Documentation From Texas Instruments Read This First Notational Conventions Notational Conventions Features Not Supported FeaturesPurpose of the Peripheral Cppi Functional Block Diagram Example 1. Initializing the USB Controller Supported Use Case Examples Example 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement USB Pins Signal DescriptionsClock Control Indexed and Non-Indexed Registers Dynamic Fifo Sizing USB PHY Initialization Interrupt Service Routine Flow Chart Peripheral Mode Control Transactions USB Controller Peripheral Mode Operation Write Requests Zero Data Requests Read Requests Endpoint 0 States CPU Actions at Transfer Phases OUT Sequence of Transfer Endpoint 0 Service Routine = Idle Service Endpoint 0 Flow Chart Idle Mode Flow Chart Idle Mode TX Mode Flow Chart TX Mode RX Mode Flow Chart RX Mode Additional Conditions Error Handling Setup Peripheral Mode Bulk In TransactionsBit Position Bit Field Name Configuration Bulk Transactions Operation Peripheral Mode Bulk OUT Transactions Disnyet Interrupt Transactions Isochronous in Transactions Isochronous Transactions Isochronous OUT Transactions Set to 1 to enable isochronous protocol Host Mode Control Transactions USB Controller Host Mode Operation Setup Phase of a Control Transaction Flow Chart Setup Phase Rxpktrdy Data Phase OUT Data Phase Data Phase Flow Chart OUT Data Phase Flow Chart Completion of Setup or OUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data Phase OUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions DMA Transmit Operation DMA OperationTransmit Buffer Cppi Transmit Buffer Descriptor Bits Name Description Transmit Buffer Descriptor WordBits Name Description 310 Buffer Pointer Descriptor. The software sets the Buffer Pointer EOQ Transmit DMA State Operation Transmit Queue Transparent Mode and Rndis Mode Transmit DMA Operation Transparent Mode Setup Rndis Mode SetupDMA Channel TearDown DMA Receive Operation Receive Buffer Descriptor Word Cppi Receive Buffer Descriptor Bit Field Receive DMA State Receive Queue Rx Queue Flow Chart USB Controller Host and Peripheral Modes Operation Receive Abort Handling Rndis Mode and Transparent Mode Receive DMA Operation Interrupt Handling DMA Teardown ProcedureInterrupts Generated by the USB Controller USB Interrupt Conditions USB Interrupt Conditions USB Core Interrupts Test ModesDMA Interrupts Testj TESTSE0NAKTestk Testpacket Forcehost Power Management Reset ConsiderationsInterrupt Support Edma Event Support Acronym Register Description Universal Serial Bus USB RegistersTransmit/Receive Cppi Channel 0 State Block Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint Target Endpoint 4 Control Registers, Valid Only in Host Mode 51Dh Control Register Ctrlr Field Descriptions Control Register CtrlrBit Field Value Description Rndis Register Rndisr Status Register StatrStatus Register Statr Field Descriptions Rndis Register Rndisr Field Descriptions Auto Request Register Autoreq Field Descriptions Auto Request Register Autoreq USB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Register IntsrcrUSB USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register Intsetr USB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register Intclrr USB Interrupt Mask Register Intmskr Field Descriptions USB Interrupt Mask Register Intmskr USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register Intmaskedr USB Interrupt Vector Register Intvectr USB End of Interrupt Register EoirUSB End of Interrupt Register Eoir Field Descriptions USB Interrupt Vector Register Intvectr Field Descriptions Transmit Cppi Teardown Register Tcppitdr Transmit Cppi Control Register TcppicrTransmit Cppi Control Register Tcppicr Field Descriptions Transmit Cppi Teardown Register Tcppitdr Field Descriptions Cppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register Cppieoir Transmit Cppi Raw Status Register Tcppirawsr Transmit Cppi Masked Status Register TcppimsksrMasked Comppending Comppending Transmit Cppi Interrupt Enable Clear Register Tcppiienclrr Transmit Cppi Interrupt Enable Set Register TcppiiensetrComppendingintren Receive Cppi Control Register Rcppicr RcppienableReceive Cppi Masked Status Register Rcppimsksr Receive Cppi Control Register Rcppicr Field Descriptions Receive Cppi Raw Status Register Rcppirawsr Receive Cppi Interrupt Enable Set Register Rcppiensetr Receive Buffer Count 0 Register RBUFCNT0 Receive Cppi Interrupt Enable Clear Register RcppiienclrrReceive Buffer Count 0 Register RBUFCNT0 Field Descriptions Bufcnt Receive Buffer Count 2 Register RBUFCNT2 Receive Buffer Count 1 Register RBUFCNT1Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Receive Buffer Count 2 Register RBUFCNT2 Field Descriptions Transmit Cppi DMA State Word 0 TCPPIDMASTATEW0 Receive Buffer Count 3 Register RBUFCNT3Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions Txqheadptr Transmit Cppi DMA State Word 2 TCPPIDMASTATEW2 Transmit Cppi DMA State Word 1 TCPPIDMASTATEW1Sopdescriptorptr Currdescriptorptr Truncatednoneop Transmit Cppi DMA State Word 4 TCPPIDMASTATEW4 Transmit Cppi DMA State Word 3 TCPPIDMASTATEW3 Transmit Cppi Completion Pointer Tcppicompptr Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5 Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Sopbufferoffset Rxqheadptr Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Receive Cppi DMA State Word 3 RCPPIDMASTATEW3 Receive Cppi DMA State Word 2 RCPPIDMASTATEW2 108 Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Pktlength Receive Cppi Completion Pointer Rcppicompptr Receive Cppi DMA State Word 6 RCPPIDMASTATEW6Sopbufferbytecnt Currbufferbytecnt Power Management Register Power Field Descriptions Power Management Register PowerReadback / Compare Mode Function Address Register Faddr Field Descriptions Interrupt Register for Receive Endpoints 1 to 4 IntrrxEP4TX EP3TX EP2TX EP1TX EP0 EP4TX Interrupt Enable Register for Intrrx Intrrxe Interrupt Enable Register for Intrtx IntrtxeEP4RX EP3RX EP2RX EP1RX EP4RX Interrupt Enable Register for Intrrx Intrrxe Interrupt Register for Common USB Interrupts Intrusb Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendVbuserr Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb Intrusbe Frame Number Register Frame Field Descriptions Frame Number Register FrameFramenumber Epsel Forcehost Register to Enable the USB 2.0 Test Modes TestmodeForcefs Forcehs Maxpayload Setupend ServsetupendFlushfifo Servrxpktrdy Datatog Datatogwren Clrdatatog ISO Mode Dmaen Frcdatatog Dmamode Control Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Control Status Register for Host Receive Endpoint Hostrxcsr DataerrnaktimeoutDmaen Disnyet Dmamode Datatogwren 127 Receive Count Register Rxcount Count 0 Register COUNT0Count 0 Register COUNT0 Field Descriptions Receive Count Register Rxcount Field Descriptions Transmit Type Register Host mode only Hosttxtype Type Register Host mode only HOSTTYPE0Type Register Host mode only HOSTTYPE0 Field Descriptions Speed Transmit Interval Register Host mode only Hosttxinterval NAKLimit0 Register Host mode only HOSTNAKLIMIT0EP0NAKLIMIT Polintvlnaklimit Receive Interval Register Host mode only Hostrxinterval Receive Type Register Host mode only HostrxtypeSpeed Prot Rendpn Configuration Data Register Configdata Field Descriptions Configuration Data Register ConfigdataMprxe 133 Data Transmit and Receive Fifo Register for Endpoint 0 FIFO0 Transmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 1 FIFO1Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 4 FIFO4 Transmit and Receive Fifo Register for Endpoint 3 FIFO3 OTG Device Control Register Devctl Field Descriptions OTG Device Control Register DevctlBdevice Fsdev Lsdev Vbus Hostmode Hostreq Session Bdevice Receive Endpoint Fifo Size Rxfifosz Transmit Endpoint Fifo Size TxfifoszTransmit Endpoint Fifo Size Txfifosz Field Descriptions Receive Endpoint Fifo Size Rxfifosz Field Descriptions Receive Endpoint Fifo Address Rxfifoaddr Transmit Endpoint Fifo Address TxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Field Descriptions Addr Transmit Hub Address Txhubaddr Transmit Function Address TxfuncaddrTransmit Hub Port Txhubport Receive Hub Address Rxhubaddr Receive Function Address RxfuncaddrReceive Hub Port Rxhubport 142 Additions/Modifications/Deletions Table A-1. Document Revision History DSP Products ApplicationsRfid