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USB Controller Host and Peripheral Modes Operation | www.ti.com |
Figure 4. Sequence of Transfer
Idle
TX state Idle
Sequence #1 | Setup | Int |
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Unload device
CPU actions req. and clear RxPktRdy
Idle
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| IN data |
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| Int |
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| Load FIFO |
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| Load FIFO |
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| Load FIFO and | ||||||||
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| and set |
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| and set |
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| set TxPktRdy | |||||||
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| TxPktRdy |
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| TxPktRdy |
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| and set DataEnd |
RX state
Status phase
(OUT)
Idle
Int
Sequence #2 | Setup |
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CPU actions
Int
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| OUT data |
| Int |
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| Int | OUT data |
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| Unload |
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| Unload FIFO |
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| device req. |
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| and clear |
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| and clear |
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| RxPktRdy |
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| RxPktRdy |
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Status phase |
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Unload FIFO and clear RxPktRdy and set DataEnd
No data phase
Sequence #3 | Setup |
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Idle
CPU actions
Int |
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| Status phase |
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| Unload device req and | |||
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| clear RxPktRdy and set | |||
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| DataEnd |
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30 | Universal Serial Bus (USB) Controller |