USB Controller Host and Peripheral Modes Operation | www.ti.com |
3.At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL is set, it indicates that the target did not accept the command (e.g., because it is not supported by the target device) and so has issued a STALL response.
If ERROR is set, it means that the controller has tried to send the SETUP Packet and the following data packet three times without getting any response.
If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt to send the SETUP packet, for longer than the time set in HOST_NAKLIMIT0. The controller can then be directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.
4.If none of RXSTALL, ERROR or NAK_TIMEOUT is set, the SETUP Phase has been correctly ACKed and the software should proceed to the following IN Data Phase, OUT Data Phase or IN Status Phase specified for the particular Standard Device Request.
3.2.1.2IN Data Phase
For the IN Data Phase of a control transaction (Figure 10), the software driving the USB host device needs to:
1.Set REQPKT bit of HOST_CSR0 (bit 5).
2.Wait while the controller sends the IN token and receives the required data back.
3.When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0) has been set.
If RXSTALL is set, it indicates that the target has issued a STALL response.
If ERROR is set, it means that the controller has tried to send the required IN token three times without getting any response.
If NAK_TIMEOUT bit is set, it means that the controller has received a NAK response to each attempt to send the IN token, for longer than the time set in HOST_NAKLIMIT0. The controller can then be directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT before clearing the NAK_TIMEOUT bit.
4.If RXPKTRDY has been set, the software should read the data from the Endpoint 0 FIFO, then clear
RXPKTRDY.
5.If further data is expected, the software should repeat Steps
When all the data has been successfully received, the CPU should proceed to the OUT Status Phase of the Control Transaction.
46 | Universal Serial Bus (USB) Controller |
