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4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
The Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) is shown in Figure 40 and described in Table 41.
Figure 40. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
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| 16 |
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| Reserved |
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15 |
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| 4 | 3 | 0 |
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| Reserved | COMP_PENDING_INTR_EN | ||
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LEGEND: R/W = Read/Write; R = Read only; |
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| Table 41. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions | ||||
Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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COMP_PENDING_INTR_EN | Receive CPPI Interrupt Enables |
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| These are active high interrupt enables corresponding to the Receive CPPI |
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| Completion Pending status bits. Writing a 1 to any of the bits in the Receive CPPI | ||
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| Interrupt Enable Clear Register will result in clearing of the corresponding bit in the | ||
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| Receive CPPI Interrupt Enable Register. |
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4.26 Receive Buffer Count 0 Register (RBUFCNT0)
The Receive Buffer Count 0 Register (RBUFCNT0) is shown in Figure 41 and described in Table 42.
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| Figure 41. Receive Buffer Count 0 Register (RBUFCNT0) | |
31 |
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| 16 |
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| Reserved |
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15 |
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| 0 |
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| BUFCNT |
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LEGEND: R/W = Read/Write; R = Read only; | |||
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| Table 42. Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions | |
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
BUFCNT | Receive CPPI Buffer Count | ||
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| The current count of CPPI buffers in Receive channel 0 queue. Writes add to current value (not |
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| overwrite). The DMA requires a minimum of 3 RX buffers to operate. |
Universal Serial Bus (USB) Controller | 99 | |
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