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www.ti.com | USB Controller Host and Peripheral Modes Operation |
| Figure 13. Completion of IN Data Phase Flow Chart | |||||
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| Completion of |
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| IN data phase |
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| TxPktRdy | No |
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| and StatusPkt |
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| both set |
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| ? |
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| Yes |
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| OUT token sent |
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| Zero−length |
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| DATA1 packet sent |
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| Stall |
| RxStall set | Command could |
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| Yes | not be completed | ||
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| TxPktRdy cleared | |||
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| received |
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| Error Count cleared |
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| ? |
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| interrupt generated |
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| No |
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| ACK | Yes | TxPktRdy cleared |
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| received | Error Count cleared |
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| ? |
| Interrupt generated |
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| No |
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| Transaction |
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No | NAK limit | Yes | NAK |
| complete |
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reached | received |
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| ? |
| ? |
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Error count |
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| No |
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cleared |
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| Yes |
| Error count |
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| NAK Timeout set |
| incremented |
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| Endpoint halted |
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| Interrupt generated |
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| Implies problem |
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| Error |
| Error bit set | at peripheral end |
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| No | Yes | of connection. | ||
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| TxPktRdy cleared | ||||
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| count=3 |
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| Error Count cleared |
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| ? |
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| interrupt generated |
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| Transaction deemed |
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| complete |
Universal Serial Bus (USB) Controller | 51 | |
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