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4.16 CPPI DMA End of Interrupt Register (CPPIEOIR)
Note: This register was previously named TCPPIEOIR, and that name will continue to exist in the CSL for backward compatibility.
The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in Figure 31 and described in Table 32.
Figure 31. CPPI DMA End of Interrupt Register (CPPIEOIR)
31 |
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| 16 |
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| Reserved |
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15 |
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| 8 | 7 | 0 |
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| Reserved |
| VECTOR | |
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LEGEND: R/W = Read/Write; R = Read only; |
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| Table 32. CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions | |||
Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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VECTOR | End of Interrupt Vector |
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This is an application specific register which is essentially a general purpose output from the LCSAR. One cycle after this register is written, the eoi_vector[7:0] value will appear on the eoi_vector output port from the LCSAR and the eoi_write output port will be asserted for 1 clock cycle. This register is used to convert level sensitive interrupts to pulsed,
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