Texas Instruments TMS320DM357 guide

Registers

www.ti.com

4.16 CPPI DMA End of Interrupt Register (CPPIEOIR)

Note: This register was previously named TCPPIEOIR, and that name will continue to exist in the CSL for backward compatibility.

The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in Figure 31 and described in Table 32.

Figure 31. CPPI DMA End of Interrupt Register (CPPIEOIR)

31					16
			Reserved
				R-0
15			8	7	0
		Reserved			VECTOR
		R-0			R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
		Table 32. CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions
Bit	Field	Value	Description
31-8	Reserved	0	Reserved
7-0	VECTOR	0-FFh	End of Interrupt Vector

This is an application specific register which is essentially a general purpose output from the LCSAR. One cycle after this register is written, the eoi_vector[7:0] value will appear on the eoi_vector output port from the LCSAR and the eoi_write output port will be asserted for 1 clock cycle. This register is used to convert level sensitive interrupts to pulsed, non-redundant interrupts. Software should write all zeros for the vector value.

94

Universal Serial Bus (USB) Controller

SPRUGH3–November 2008

Submit Documentation Feedback

Image 94

Texas Instruments TMS320DM357 manual Cppi DMA End of Interrupt Register Cppieoir

Contents

Users Guide Submit Documentation Feedback Contents 100 Type Register Host mode only HOSTTYPE0 Appendix a List of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Read This First Related Documentation From Texas Instruments Notational Conventions Notational Conventions Features Not Supported FeaturesPurpose of the Peripheral Functional Block Diagram Cppi Supported Use Case Examples Example 1. Initializing the USB Controller Example 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement Clock Control Signal DescriptionsUSB Pins Indexed and Non-Indexed Registers USB PHY Initialization Dynamic Fifo Sizing Interrupt Service Routine Flow Chart USB Controller Peripheral Mode Operation Peripheral Mode Control Transactions Zero Data Requests Write Requests Read Requests CPU Actions at Transfer Phases Endpoint 0 States Sequence of Transfer OUT Endpoint 0 Service Routine Service Endpoint 0 Flow Chart = Idle Idle Mode Idle Mode Flow Chart TX Mode TX Mode Flow Chart RX Mode RX Mode Flow Chart Error Handling Additional Conditions Bit Position Bit Field Name Configuration Peripheral Mode Bulk In TransactionsSetup Bulk Transactions Peripheral Mode Bulk OUT Transactions Operation Disnyet Interrupt Transactions Isochronous Transactions Isochronous in Transactions Isochronous OUT Transactions Set to 1 to enable isochronous protocol USB Controller Host Mode Operation Host Mode Control Transactions Setup Phase Setup Phase of a Control Transaction Flow Chart Data Phase Rxpktrdy Data Phase Flow Chart OUT Data Phase OUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data Phase Completion of Setup or OUT Data Phase Flow Chart OUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions Transmit Buffer DMA OperationDMA Transmit Operation Cppi Transmit Buffer Descriptor Bits Name Description 310 Buffer Pointer Transmit Buffer Descriptor WordBits Name Description Descriptor. The software sets the Buffer Pointer Transmit DMA State EOQ Transmit Queue Operation Transparent Mode and Rndis Mode Transmit DMA Operation DMA Channel TearDown Rndis Mode SetupTransparent Mode Setup DMA Receive Operation Cppi Receive Buffer Descriptor Receive Buffer Descriptor Word Receive DMA State Bit Field Rx Queue Flow Chart Receive Queue USB Controller Host and Peripheral Modes Operation Rndis Mode and Transparent Mode Receive DMA Operation Receive Abort Handling Interrupts Generated by the USB Controller DMA Teardown ProcedureInterrupt Handling USB Interrupt Conditions USB Interrupt Conditions USB Core Interrupts Test ModesDMA Interrupts Testj TESTSE0NAKTestk Testpacket Forcehost Interrupt Support Reset ConsiderationsPower Management Edma Event Support Acronym Register Description Universal Serial Bus USB RegistersTransmit/Receive Cppi Channel 0 State Block Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Target Endpoint 4 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint 51Dh Control Register Ctrlr Field Descriptions Control Register CtrlrBit Field Value Description Status Register Statr Field Descriptions Status Register StatrRndis Register Rndisr Rndis Register Rndisr Field Descriptions Auto Request Register Autoreq Auto Request Register Autoreq Field Descriptions USB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Register IntsrcrUSB USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register Intsetr USB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register Intclrr USB Interrupt Mask Register Intmskr USB Interrupt Mask Register Intmskr Field Descriptions USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register Intmaskedr USB End of Interrupt Register Eoir Field Descriptions USB End of Interrupt Register EoirUSB Interrupt Vector Register Intvectr USB Interrupt Vector Register Intvectr Field Descriptions Transmit Cppi Control Register Tcppicr Field Descriptions Transmit Cppi Control Register TcppicrTransmit Cppi Teardown Register Tcppitdr Transmit Cppi Teardown Register Tcppitdr Field Descriptions Cppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register Cppieoir Masked Comppending Transmit Cppi Masked Status Register TcppimsksrTransmit Cppi Raw Status Register Tcppirawsr Comppending Transmit Cppi Interrupt Enable Clear Register Tcppiienclrr Transmit Cppi Interrupt Enable Set Register TcppiiensetrComppendingintren Receive Cppi Masked Status Register Rcppimsksr RcppienableReceive Cppi Control Register Rcppicr Receive Cppi Control Register Rcppicr Field Descriptions Receive Cppi Interrupt Enable Set Register Rcppiensetr Receive Cppi Raw Status Register Rcppirawsr Receive Buffer Count 0 Register RBUFCNT0 Field Descriptions Receive Cppi Interrupt Enable Clear Register RcppiienclrrReceive Buffer Count 0 Register RBUFCNT0 Bufcnt Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Receive Buffer Count 1 Register RBUFCNT1Receive Buffer Count 2 Register RBUFCNT2 Receive Buffer Count 2 Register RBUFCNT2 Field Descriptions Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions Receive Buffer Count 3 Register RBUFCNT3Transmit Cppi DMA State Word 0 TCPPIDMASTATEW0 Txqheadptr Sopdescriptorptr Transmit Cppi DMA State Word 1 TCPPIDMASTATEW1Transmit Cppi DMA State Word 2 TCPPIDMASTATEW2 Currdescriptorptr Truncatednoneop Transmit Cppi DMA State Word 3 TCPPIDMASTATEW3 Transmit Cppi DMA State Word 4 TCPPIDMASTATEW4 Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5 Transmit Cppi Completion Pointer Tcppicompptr Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Sopbufferoffset Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Rxqheadptr Receive Cppi DMA State Word 2 RCPPIDMASTATEW2 Receive Cppi DMA State Word 3 RCPPIDMASTATEW3 108 Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Pktlength Sopbufferbytecnt Receive Cppi DMA State Word 6 RCPPIDMASTATEW6Receive Cppi Completion Pointer Rcppicompptr Currbufferbytecnt Readback / Compare Mode Power Management Register PowerPower Management Register Power Field Descriptions Function Address Register Faddr EP4TX EP3TX EP2TX EP1TX EP0 Interrupt Register for Receive Endpoints 1 to 4 IntrrxField Descriptions EP4TX EP4RX EP3RX EP2RX EP1RX Interrupt Enable Register for Intrtx IntrtxeInterrupt Enable Register for Intrrx Intrrxe EP4RX Interrupt Enable Register for Intrrx Intrrxe Interrupt Register for Common USB Interrupts Intrusb Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendVbuserr Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb Intrusbe Framenumber Frame Number Register FrameFrame Number Register Frame Field Descriptions Epsel Forcefs Register to Enable the USB 2.0 Test Modes TestmodeForcehost Forcehs Maxpayload Flushfifo ServsetupendSetupend Servrxpktrdy Datatogwren Datatog ISO Mode Dmaen Frcdatatog Dmamode Clrdatatog Control Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Control Status Register for Host Receive Endpoint Hostrxcsr DataerrnaktimeoutDmaen Disnyet Dmamode Datatogwren 127 Count 0 Register COUNT0 Field Descriptions Count 0 Register COUNT0Receive Count Register Rxcount Receive Count Register Rxcount Field Descriptions Type Register Host mode only HOSTTYPE0 Field Descriptions Type Register Host mode only HOSTTYPE0Transmit Type Register Host mode only Hosttxtype Speed EP0NAKLIMIT NAKLimit0 Register Host mode only HOSTNAKLIMIT0Transmit Interval Register Host mode only Hosttxinterval Polintvlnaklimit Receive Interval Register Host mode only Hostrxinterval Receive Type Register Host mode only HostrxtypeSpeed Prot Rendpn Configuration Data Register Configdata Field Descriptions Configuration Data Register ConfigdataMprxe 133 Transmit and Receive Fifo Register for Endpoint 0 FIFO0 Data Transmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 1 FIFO1Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 3 FIFO3 Transmit and Receive Fifo Register for Endpoint 4 FIFO4 Bdevice Fsdev Lsdev Vbus Hostmode Hostreq Session OTG Device Control Register DevctlOTG Device Control Register Devctl Field Descriptions Bdevice Transmit Endpoint Fifo Size Txfifosz Field Descriptions Transmit Endpoint Fifo Size TxfifoszReceive Endpoint Fifo Size Rxfifosz Receive Endpoint Fifo Size Rxfifosz Field Descriptions Receive Endpoint Fifo Address Rxfifoaddr Field Descriptions Transmit Endpoint Fifo Address TxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Addr Transmit Hub Address Txhubaddr Transmit Function Address TxfuncaddrTransmit Hub Port Txhubport Receive Hub Address Rxhubaddr Receive Function Address RxfuncaddrReceive Hub Port Rxhubport 142 Table A-1. Document Revision History Additions/Modifications/Deletions DSP Products ApplicationsRfid