www.ti.comUSB Controller Host and Peripheral Modes Operation
Table 9. Transmit Buffer Descriptor Word 3 (continued)
Bits | Name | Value | Description |
28 | EOQ |
| End of Queue: The End of Queue bit is set by the DMA controller to indicate that all packets |
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| in the queue have been transmitted and the Tx queue is empty. This bit is valid only on when |
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| EOP is set. |
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| 0 | The Tx queue has more packets to transfer |
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| 1 | The DMA controller took this descriptor buffer as the last buffer descriptor in the last packet in |
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| the queue |
27:24 | Reserved |
| Reserved |
23 | Zero Byte |
| Zero Byte Packet Identifier. This bit is set by the software when a zero byte USB packet |
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| needs to be transmitted. This bit tells the DMA controller that no data transfer needs to be |
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| done for transmitting this zero byte data buffer. Set the Packet Length to 1 when setting this |
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| bit. |
22:16 | Reserved |
| Reserved |
15:0 | Packet Length |
| The length of the DMA packet in bytes. This field is valid only on SOP and is written by the |
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| software. If the Packet Length is less than the sum of the buffer lengths, then the packet data |
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| will be truncated. A Packet Length greater than the sum of the buffers is a software error. |
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| Packet Length must be nonzero. Set to one when setting the Zero Byte bit. |
Four different cases are possible for the number of buffers in a DMA packet:
1.Buffer Descriptor contains Start of Packet field and End of Packet field (1 buffer in DMA packet).
2.Buffer Descriptor contains Start of Packet field only (2+ buffers in DMA packet).
3.Buffer Descriptor contains End of Packet field only (2+ buffers in DMA packet).
4.Buffer Descriptor does not contain either of Start of Packet field and End of Packet field (3+ buffers in packet).
3.3.1.3Transmit DMA State
The DMA controller stores and maintains state information for each transmit channel. The state information is referred to as the Tx DMA State. The Tx DMA State is a combination of control fields and DMA controller specific scratchpad space used to manipulate data structures and transmit DMA packets. The Tx DMA State is stored in registers TCPPIDMASTATEW0, TCPPIDMASTATEW1, TCPPIDMASTATEW2, TCPPIDMASTATEW3, TCPPIDMASTATEW4, TCPPIDMASTATEW5 and TCPPICOMPPTR for each channel.
Each channel has one queue. The queue has one head descriptor pointer and one completion pointer.
The following information is stored in the Tx DMA State:
∙TCPPIDMASTATEW0: Tx Queue Head Descriptor Pointer(s)
∙TCPPICOMPPTR: Tx Completion Pointer(s)
∙TCPPIDMASTATEW1: Start of Packet Buffer Descriptor Pointer
∙TCPPIDMASTATEW2: Current Buffer Descriptor Pointer
∙TCPPIDMASTATEW3: Current Buffer Pointer
∙TCPPIDMASTATEW5: Remaining DMA Packet Length and Actual DMA Packet Length
Universal Serial Bus (USB) Controller | 59 |
