Texas Instruments TMS320DM357 manual ISO Mode Dmaen Frcdatatog Dmamode, Clrdatatog

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4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)

The Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) is shown in Figure 74 and described in Table 75.

Figure 74. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)

15		14		13	12	11	10	9	7
Reserved		ISO		MODE	DMAEN	FRCDATATOG	DMAMODE		Reserved
R-0		R/W-0		R/W-0	R/W-0	R/W-0	R/W-0		R-0
6		5		4	3	2	1		0
CLRDATATOG		SENTSTALL	SENDSTALL		FLUSHFIFO	UNDERRUN	FIFONOTEMPTY		TXPKTRDY
W-0		R/W-0		R/W-0	W-0	R/W-0	R/W-0		R/W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n= value after reset
		Table 75. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
					Field Descriptions
Bit	Field		Value	Description
15	Reserved		0	Reserved
14	ISO		0-1	Set this bit to enable the Tx endpoint for Isochronous transfers, and clear this bit to enable the Tx
				endpoint for Bulk or Interrupt transfers.
13	MODE		0-1	Set this bit to enable the endpoint direction as Tx, and clear this bit to enable it as Rx.
				Note: This bit has any effect only where the same endpoint FIFO is used for both Transmit and
				Receive transactions.
12	DMAEN		0-1	Set this bit to enable the DMA request for the Tx endpoint.
11	FRCDATATOG		0-1	Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the
				FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints
				that are used to communicate rate feedback for Isochronous endpoints.
10	DMAMODE		0-1	When using DMA, clear this bit to receive an interrupt for each packet, or set this bit to only
				receive error interrupts.
9-7	Reserved		0	Reserved
6	CLRDATATOG		0-1	Set this bit to reset the endpoint data toggle to 0.
5	SENTSTALL		0-1	This bit is set automatically when a STALL handshake is transmitted. The FIFO is flushed and the
				TXPKTRDY bit is cleared. You should clear this bit.
4	SENDSTALL		0-1	Set this bit to issue a STALL handshake to an IN token. Clear this bit to terminate the stall
				condition.
				Note: This bit has no effect where the endpoint is being used for Isochronous transfers.
3	FLUSHFIFO		0-1	Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer
				is reset and the TXPKTRDY bit is cleared.
				Note: FlushFIFO has no effect unless TXPKTRDY is set. Also note that, if the FIFO is
				double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
2	UNDERRUN		0-1	This bit is set automatically if an IN token is received when TXPKTRDY is not set. You should
				clear this bit.
1	FIFONOTEMPTY		0-1	This bit is set when there is at least 1 packet in the Tx FIFO. You should clear this bit.
0	TXPKTRDY		0-1	Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet
				has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.

122 Universal Serial Bus (USB) Controller SPRUGH3–November 2008

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