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4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
The Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) is shown in Figure 74 and described in Table 75.
Figure 74. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
15 |
| 14 |
| 13 | 12 | 11 | 10 | 9 | 7 |
Reserved | ISO |
| MODE | DMAEN | FRCDATATOG | DMAMODE |
| Reserved | |
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6 |
| 5 |
| 4 | 3 | 2 | 1 |
| 0 |
CLRDATATOG | SENTSTALL | SENDSTALL | FLUSHFIFO | UNDERRUN | FIFONOTEMPTY | TXPKTRDY | |||
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LEGEND: R/W = Read/Write; R = Read only; W = Write only; |
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| Table 75. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) | |||||||
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| Field Descriptions |
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Bit | Field |
| Value | Description |
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15 | Reserved | 0 | Reserved |
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14 | ISO |
| Set this bit to enable the Tx endpoint for Isochronous transfers, and clear this bit to enable the Tx | ||||||
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| endpoint for Bulk or Interrupt transfers. |
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13 | MODE |
| Set this bit to enable the endpoint direction as Tx, and clear this bit to enable it as Rx. | ||||||
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| Note: This bit has any effect only where the same endpoint FIFO is used for both Transmit and | |||||
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| Receive transactions. |
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12 | DMAEN |
| Set this bit to enable the DMA request for the Tx endpoint. |
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11 | FRCDATATOG | Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the | |||||||
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| FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints | |||||
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| that are used to communicate rate feedback for Isochronous endpoints. |
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10 | DMAMODE | When using DMA, clear this bit to receive an interrupt for each packet, or set this bit to only | |||||||
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| receive error interrupts. |
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Reserved | 0 | Reserved |
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6 | CLRDATATOG | Set this bit to reset the endpoint data toggle to 0. |
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5 | SENTSTALL | This bit is set automatically when a STALL handshake is transmitted. The FIFO is flushed and the | |||||||
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| TXPKTRDY bit is cleared. You should clear this bit. |
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4 | SENDSTALL | Set this bit to issue a STALL handshake to an IN token. Clear this bit to terminate the stall | |||||||
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| Note: This bit has no effect where the endpoint is being used for Isochronous transfers. | |||||
3 | FLUSHFIFO | Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer | |||||||
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| is reset and the TXPKTRDY bit is cleared. |
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| Note: FlushFIFO has no effect unless TXPKTRDY is set. Also note that, if the FIFO is | |||||
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2 | UNDERRUN | This bit is set automatically if an IN token is received when TXPKTRDY is not set. You should | |||||||
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| clear this bit. |
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1 | FIFONOTEMPTY | This bit is set when there is at least 1 packet in the Tx FIFO. You should clear this bit. | |||||||
0 | TXPKTRDY | Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet | |||||||
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| has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. |
122 | Universal Serial Bus (USB) Controller |