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| List of Tables |
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| 1 | USB Pins | 23 |
| 2 | PERI_TXCSR Register Bit Configuration for Bulk IN Transactions | 37 |
| 3 | PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions | 39 |
| 4 | PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions | 41 |
| 5 | PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions | 43 |
| 6 | Transmit Buffer Descriptor Word 0 | 58 |
| 7 | Transmit Buffer Descriptor Word 1 | 58 |
| 8 | Transmit Buffer Descriptor Word 2 | 58 |
| 9 | Transmit Buffer Descriptor Word 3 | 58 |
| 10 | Receive Buffer Descriptor Word 0 | 63 |
| 11 | Receive Buffer Descriptor Word 1 | 63 |
| 12 | Receive Buffer Descriptor Word 2 | 63 |
| 13 | Receive Buffer Descriptor Word 3 | 64 |
| 14 | Interrupts Generated by the USB Controller | 68 |
| 15 | USB Interrupt Conditions | 68 |
| 16 | Universal Serial Bus (USB) Registers | 75 |
| 17 | Control Register (CTRLR) Field Descriptions | 82 |
| 18 | Status Register (STATR) Field Descriptions | 83 |
| 19 | RNDIS Register (RNDISR) Field Descriptions | 83 |
| 20 | Auto Request Register (AUTOREQ) Field Descriptions | 84 |
| 21 | USB Interrupt Source Register (INTSRCR) Field Descriptions | 85 |
| 22 | USB Interrupt Source Set Register (INTSETR) Field Descriptions | 86 |
| 23 | USB Interrupt Source Clear Register (INTCLRR) Field Descriptions | 87 |
| 24 | USB Interrupt Mask Register (INTMSKR) Field Descriptions | 88 |
| 25 | USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions | 89 |
| 26 | USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions | 90 |
| 27 | USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions | 91 |
| 28 | USB End of Interrupt Register (EOIR) Field Descriptions | 92 |
| 29 | USB Interrupt Vector Register (INTVECTR) Field Descriptions | 92 |
| 30 | Transmit CPPI Control Register (TCPPICR) Field Descriptions | 93 |
| 31 | Transmit CPPI Teardown Register (TCPPITDR) Field Descriptions | 93 |
| 32 | CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions | 94 |
| 33 | Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions | 95 |
| 34 | Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions | 95 |
| 35 | Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions | 96 |
| 36 | Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions | 96 |
| 37 | Receive CPPI Control Register (RCPPICR) Field Descriptions | 97 |
| 38 | Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions | 97 |
| 39 | Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions | 98 |
| 40 | Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions | 98 |
| 41 | Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions | 99 |
| 42 | Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions | 99 |
| 43 | Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions | 100 |
| 44 | Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions | 100 |
| 45 | Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions | 101 |
| 46 | Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions | 101 |
| 47 | Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) Field Descriptions | 102 |
| 48 | Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions | 102 |
| 49 | Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) Field Descriptions | 103 |
8 | List of Tables | ||
