USB Controller Host and Peripheral Modes Operation | www.ti.com |
3.3.1.4Transmit Queue
Figure 14 shows a Tx queue. Tx queue provide a logical queue of DMA packets for transmission through a channel. Each channel has one dedicated Tx queues. The queue has one associated Tx Queue Head Descriptor Pointer and one associated Tx Completion Pointer container in the channel Tx DMA state. The Tx queue is linked lists of Tx buffer descriptors that constitute one or more packets queued for transmission. Packets are added to the tail of the list by the software and packets are freed from the head of the list by the DMA controller as each packet transmission is completed.
Figure 14. Tx Queue Flow Chart
SOP descriptor
Descriptor
EOP descriptor
Buffer
Buffer
Buffer
Tx queue head descriptor pointer
3.3.1.5Operation
∙After reset the software must write zeroes to all Tx DMA State registers (TCPPIDMASTATEW0, TCPPIDMASTATEW1, TCPPIDMASTATEW2, TCPPIDMASTATEW3, TCPPIDMASTATEW4, TCPPIDMASTATEW5).
∙The software constructs transmit queues in memory (one or more DMA packets for transmission)
∙Enable DMA for the endpoint in the PERI_TXCSR or HOST_TXCSR by setting the DMAEN bit.
∙Enable the DMA ports by setting TCPPI_ENABLE bit of TCPPICR register.
∙Write the head of the queue descriptor pointer to the TCPPIDMASTATEW0 register to start the DMA.
∙The USB controller will start transmitting data. Interrupt associated with the DMA channel is asserted, after each DMA packet is transmitted.
For each buffer added to a transmit queue, the software must initialize the Tx buffer descriptor values as follows:
∙Write the Next Descriptor Pointer with the
∙Write the Buffer Pointer with the byte aligned address of the buffer data
∙Write the Buffer Length with the number of bytes in the buffer
∙Write the Buffer Offset with the number of bytes in the offset to the data (nonzero with SOP only)
∙Set the SOP, EOP, and Ownership bits as appropriate
∙Clear the End Of Queue bit
The DMA controller begins Tx DMA packet transmission on a given channel when the host writes the channel’s Tx queue head descriptor pointer with the address of the first buffer descriptor in the queue (nonzero value). Each channel has one queue and a head descriptor pointer. The first buffer descriptor for each Tx DMA packet must have the Start of Packet (SOP) bit and the Ownership bit set to one by the software. The last buffer descriptor for each Tx DMA packet must have the End of Packet (EOP) bit set to one by the software. The DMA controller will transmit DMA packets until all queued packets have been transmitted and the queue is empty. When each packet transmission is complete, the DMA controller will
60 | Universal Serial Bus (USB) Controller |
