Texas Instruments TMS320DM357 manual Endpoint 0 States, CPU Actions at Transfer Phases

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3.1.1.4Endpoint 0 States

When the USB controller is operating as a peripheral device, the endpoint 0 control needs three modes – IDLE, TX and RX – corresponding to the different phases of the control transfer and the states endpoint 0 enters for the different phases of the transfer (described in later sections).

The default mode on power-up or reset should be IDLE. RXPKTRDY bit of PERI_CSR0 (bit 0) becoming set when endpoint 0 is in IDLE state indicates a new device request. Once the device request is unloaded from the FIFO, the controller decodes the descriptor to find whether there is a data phase and, if so, the direction of the data phase of the control transfer (in order to set the FIFO direction).See Figure 3.

Depending on the direction of the data phase, endpoint 0 goes into either TX state or RX state. If there is no Data phase, endpoint 0 remains in IDLE state to accept the next device request.

The actions that the CPU needs to take at the different phases of the possible transfers (e.g., loading the FIFO, setting TXPKTRDY) are indicated in Figure 4 .

Note: The controller changes the FIFO direction, depending on the direction of the data phase independently of the CPU.

Figure 3. CPU Actions at Transfer Phases

Sequence #3

Idle

Sequence #1 Sequence #2

Tx state Rx state

SPRUGH3–November 2008 Universal Serial Bus (USB) Controller 29

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