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4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE)
The Register to Enable the USB 2.0 Test Modes (TESTMODE) is shown in Figure 70 and described in Table 71.
Figure 70. Register to Enable the USB 2.0 Test Modes (TESTMODE)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCE_HOST | FIFO_ACCESS | FORCE_FS FORCE_HS TEST_PACKET | TEST_K | TEST_J | TEST_SE0_NAK | ||
LEGEND: R/W = Read/Write; W = Write only;
Table 71. Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions
Bit | Field | Value | Description |
7 | FORCE_HOST | Set this bit to forcibly put the USB controller into Host mode when SESSION bit is set, | |
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| regardless of whether it is connected to any peripheral. The controller remains in Host mode |
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| until the Session bit is cleared, even if a device is disconnected. And if the FORCE_HOST but |
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| remains set, it will |
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| determined using the FORCE_HS and FORCE_FS bits. |
6 | FIFO_ACCESS | Set this bit to transfer the packet in EP0 Tx FIFO to EP0 Receive FIFO. It is cleared | |
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| automatically. |
5 | FORCE_FS | Set this bit to force the USB controller into | |
4 | FORCE_HS | Set this bit to force the USB controller into | |
3 | TEST_PACKET | Set this bit to enter the Test_Packet test mode. In this mode, the USB controller repetitively | |
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| transmits a |
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| Bus Specification Revision 2.0. |
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| Note: The test packet has a fixed format and must be loaded into the Endpoint 0 FIFO before |
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| the test mode is entered. |
2 | TEST_K | Set this bit to enter the Test_K test mode. In this mode, the USB controller transmits a | |
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| continuous K on the bus. |
1 | TEST_J | Set this bit to enter the Test_J test mode. In this mode, the USB controller transmits a | |
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| continuous J on the bus. |
0 | TEST_SE0_NAK | Set this bit to enter the Test_SE0_NAK test mode. In this mode, the USB controller remains in | |
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118 | Universal Serial Bus (USB) Controller |