Texas Instruments TMS320DM357 manual

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Table 16. Universal Serial Bus (USB) Registers (continued)

	Offset	Acronym	Register Description	Section
	49Eh	RXHUBADDR	Address of the hub that has to be accessed through the	Section 4.87
			associated Receive Endpoint. This is used only when full
			speed or low speed device is connected via a USB2.0
			high-speed hub.
	49Fh	RXHUBPORT	Port of the hub that has to be accessed through the	Section 4.88
			associated Receive Endpoint. This is used only when full
			speed or low speed device is connected via a USB2.0
			high-speed hub.
		Target Endpoint 4 Control Registers, Valid Only in Host Mode
	4A0h	TXFUNCADDR	Address of the target function that has to be accessed	Section 4.83
			through the associated Transmit Endpoint.
	4A2h	TXHUBADDR	Address of the hub that has to be accessed through the	Section 4.84
			associated Transmit Endpoint. This is used only when full
			speed or low speed device is connected via a USB2.0
			high-speed hub.
	4A3h	TXHUBPORT	Port of the hub that has to be accessed through the	Section 4.85
			associated Transmit Endpoint. This is used only when full
			speed or low speed device is connected via a USB2.0
			high-speed hub.
	4A4h	RXFUNCADDR	Address of the target function that has to be accessed	Section 4.86
			through the associated Receive Endpoint.
	4A6h	RXHUBADDR	Address of the hub that has to be accessed through the	Section 4.87
			associated Receive Endpoint. This is used only when full
			speed or low speed device is connected via a USB2.0
			high-speed hub.
	4A7h	RXHUBPORT	Port of the hub that has to be accessed through the	Section 4.88
			associated Receive Endpoint. This is used only when full
			speed or low speed device is connected via a USB2.0
			high-speed hub.
			Control and Status Register for Endpoint 0
	502h	PERI_CSR0	Control Status Register for Endpoint 0 in Peripheral Mode	Section 4.57
		HOST_CSR0	Control Status Register for Endpoint 0 in Host Mode	Section 4.58
	508h	COUNT0	Number of Received Bytes in Endpoint 0 FIFO	Section 4.64
	50Ah	HOST_TYPE0	Defines the Speed of Endpoint 0	Section 4.66
	50Bh	HOST_NAKLIMIT0	Sets the NAK Response Timeout on Endpoint 0	Section 4.68
	50Fh	CONFIGDATA	Returns details of core configuration.	Section 4.72
			Control and Status Register for Endpoint 1
	510h	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint	Section 4.56
	512h	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint	Section 4.59
			(peripheral mode)
		HOST_TXCSR	Control Status Register for Host Transmit Endpoint	Section 4.60
			(host mode)
	514h	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint	Section 4.61
	516h	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint	Section 4.62
			(peripheral mode)
		HOST_RXCSR	Control Status Register for Host Receive Endpoint	Section 4.63
			(host mode)
	518h	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO	Section 4.65
	51Ah	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral	Section 4.67
			endpoint number for the host Transmit endpoint.
	51Bh	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the	Section 4.69
			NAK response timeout on Bulk transactions for host Transmit
			endpoint.
	51Ch	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral	Section 4.70
			endpoint number for the host Receive endpoint.
80	Universal Serial Bus (USB) Controller		SPRUGH3–November 2008

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Texas Instruments TMS320DM357 manual Target Endpoint 4 Control Registers, Valid Only in Host Mode

Contents

Users Guide Submit Documentation Feedback Contents 100 Type Register Host mode only HOSTTYPE0 Appendix a List of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Read This First Related Documentation From Texas Instruments Notational Conventions Notational Conventions Purpose of the Peripheral FeaturesFeatures Not Supported Functional Block Diagram Cppi Supported Use Case Examples Example 1. Initializing the USB Controller Example 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement Signal Descriptions USB PinsClock Control Indexed and Non-Indexed Registers USB PHY Initialization Dynamic Fifo Sizing Interrupt Service Routine Flow Chart USB Controller Peripheral Mode Operation Peripheral Mode Control Transactions Zero Data Requests Write Requests Read Requests CPU Actions at Transfer Phases Endpoint 0 States Sequence of Transfer OUT Endpoint 0 Service Routine Service Endpoint 0 Flow Chart = Idle Idle Mode Idle Mode Flow Chart TX Mode TX Mode Flow Chart RX Mode RX Mode Flow Chart Error Handling Additional Conditions Peripheral Mode Bulk In Transactions SetupBit Position Bit Field Name Configuration Bulk Transactions Peripheral Mode Bulk OUT Transactions Operation Disnyet Interrupt Transactions Isochronous Transactions Isochronous in Transactions Isochronous OUT Transactions Set to 1 to enable isochronous protocol USB Controller Host Mode Operation Host Mode Control Transactions Setup Phase Setup Phase of a Control Transaction Flow Chart Data Phase Rxpktrdy Data Phase Flow Chart OUT Data Phase OUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data Phase Completion of Setup or OUT Data Phase Flow Chart OUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions DMA Operation DMA Transmit OperationTransmit Buffer Cppi Transmit Buffer Descriptor Transmit Buffer Descriptor Word Bits Name DescriptionBits Name Description 310 Buffer Pointer Descriptor. The software sets the Buffer Pointer Transmit DMA State EOQ Transmit Queue Operation Transparent Mode and Rndis Mode Transmit DMA Operation Rndis Mode Setup Transparent Mode SetupDMA Channel TearDown DMA Receive Operation Cppi Receive Buffer Descriptor Receive Buffer Descriptor Word Receive DMA State Bit Field Rx Queue Flow Chart Receive Queue USB Controller Host and Peripheral Modes Operation Rndis Mode and Transparent Mode Receive DMA Operation Receive Abort Handling DMA Teardown Procedure Interrupt HandlingInterrupts Generated by the USB Controller USB Interrupt Conditions USB Interrupt Conditions DMA Interrupts Test ModesUSB Core Interrupts Testk TESTSE0NAKTestj Testpacket Forcehost Reset Considerations Power ManagementInterrupt Support Edma Event Support Transmit/Receive Cppi Channel 0 State Block Universal Serial Bus USB RegistersAcronym Register Description Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Target Endpoint 4 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint 51Dh Bit Field Value Description Control Register CtrlrControl Register Ctrlr Field Descriptions Status Register Statr Rndis Register RndisrStatus Register Statr Field Descriptions Rndis Register Rndisr Field Descriptions Auto Request Register Autoreq Auto Request Register Autoreq Field Descriptions USB USB Interrupt Source Register IntsrcrUSB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register Intsetr USB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register Intclrr USB Interrupt Mask Register Intmskr USB Interrupt Mask Register Intmskr Field Descriptions USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register Intmskclrr USB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register Intmaskedr USB End of Interrupt Register Eoir USB Interrupt Vector Register IntvectrUSB End of Interrupt Register Eoir Field Descriptions USB Interrupt Vector Register Intvectr Field Descriptions Transmit Cppi Control Register Tcppicr Transmit Cppi Teardown Register TcppitdrTransmit Cppi Control Register Tcppicr Field Descriptions Transmit Cppi Teardown Register Tcppitdr Field Descriptions Cppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register Cppieoir Transmit Cppi Masked Status Register Tcppimsksr Transmit Cppi Raw Status Register TcppirawsrMasked Comppending Comppending Comppendingintren Transmit Cppi Interrupt Enable Set Register TcppiiensetrTransmit Cppi Interrupt Enable Clear Register Tcppiienclrr Rcppienable Receive Cppi Control Register RcppicrReceive Cppi Masked Status Register Rcppimsksr Receive Cppi Control Register Rcppicr Field Descriptions Receive Cppi Interrupt Enable Set Register Rcppiensetr Receive Cppi Raw Status Register Rcppirawsr Receive Cppi Interrupt Enable Clear Register Rcppiienclrr Receive Buffer Count 0 Register RBUFCNT0Receive Buffer Count 0 Register RBUFCNT0 Field Descriptions Bufcnt Receive Buffer Count 1 Register RBUFCNT1 Receive Buffer Count 2 Register RBUFCNT2Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Receive Buffer Count 2 Register RBUFCNT2 Field Descriptions Receive Buffer Count 3 Register RBUFCNT3 Transmit Cppi DMA State Word 0 TCPPIDMASTATEW0Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions Txqheadptr Transmit Cppi DMA State Word 1 TCPPIDMASTATEW1 Transmit Cppi DMA State Word 2 TCPPIDMASTATEW2Sopdescriptorptr Currdescriptorptr Truncatednoneop Transmit Cppi DMA State Word 3 TCPPIDMASTATEW3 Transmit Cppi DMA State Word 4 TCPPIDMASTATEW4 Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5 Transmit Cppi Completion Pointer Tcppicompptr Sopbufferoffset Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Rxqheadptr Receive Cppi DMA State Word 2 RCPPIDMASTATEW2 Receive Cppi DMA State Word 3 RCPPIDMASTATEW3 108 Pktlength Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Receive Cppi DMA State Word 6 RCPPIDMASTATEW6 Receive Cppi Completion Pointer RcppicompptrSopbufferbytecnt Currbufferbytecnt Power Management Register Power Power Management Register Power Field DescriptionsReadback / Compare Mode Function Address Register Faddr Interrupt Register for Receive Endpoints 1 to 4 Intrrx Field DescriptionsEP4TX EP3TX EP2TX EP1TX EP0 EP4TX Interrupt Enable Register for Intrtx Intrtxe Interrupt Enable Register for Intrrx IntrrxeEP4RX EP3RX EP2RX EP1RX EP4RX Interrupt Enable Register for Intrrx Intrrxe Vbuserr Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendInterrupt Register for Common USB Interrupts Intrusb Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb Intrusbe Frame Number Register Frame Frame Number Register Frame Field DescriptionsFramenumber Epsel Register to Enable the USB 2.0 Test Modes Testmode ForcehostForcefs Forcehs Maxpayload Servsetupend SetupendFlushfifo Servrxpktrdy Datatogwren Datatog ISO Mode Dmaen Frcdatatog Dmamode Clrdatatog Control Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Dmaen Disnyet Dmamode Datatogwren DataerrnaktimeoutControl Status Register for Host Receive Endpoint Hostrxcsr 127 Count 0 Register COUNT0 Receive Count Register RxcountCount 0 Register COUNT0 Field Descriptions Receive Count Register Rxcount Field Descriptions Type Register Host mode only HOSTTYPE0 Transmit Type Register Host mode only HosttxtypeType Register Host mode only HOSTTYPE0 Field Descriptions Speed NAKLimit0 Register Host mode only HOSTNAKLIMIT0 Transmit Interval Register Host mode only HosttxintervalEP0NAKLIMIT Polintvlnaklimit Speed Prot Rendpn Receive Type Register Host mode only HostrxtypeReceive Interval Register Host mode only Hostrxinterval Mprxe Configuration Data Register ConfigdataConfiguration Data Register Configdata Field Descriptions 133 Transmit and Receive Fifo Register for Endpoint 0 FIFO0 Data Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 1 FIFO1Transmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 3 FIFO3 Transmit and Receive Fifo Register for Endpoint 4 FIFO4 OTG Device Control Register Devctl OTG Device Control Register Devctl Field DescriptionsBdevice Fsdev Lsdev Vbus Hostmode Hostreq Session Bdevice Transmit Endpoint Fifo Size Txfifosz Receive Endpoint Fifo Size RxfifoszTransmit Endpoint Fifo Size Txfifosz Field Descriptions Receive Endpoint Fifo Size Rxfifosz Field Descriptions Transmit Endpoint Fifo Address Txfifoaddr Receive Endpoint Fifo Address RxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Field Descriptions Addr Transmit Hub Port Txhubport Transmit Function Address TxfuncaddrTransmit Hub Address Txhubaddr Receive Hub Port Rxhubport Receive Function Address RxfuncaddrReceive Hub Address Rxhubaddr 142 Table A-1. Document Revision History Additions/Modifications/Deletions Rfid Products ApplicationsDSP