Texas Instruments TMS320DM357 Function Address Register Faddr, Power Management Register Power

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Table 60. Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions (continued)

Bit	Field	Value	Description
0	RDBK_MODE		Readback / Compare Mode

0Compare Mode. Indicates that the value that is presented on bits 31:2 of the read data should be compared against the value that is currently contained in bits 31:2 of this location. If the two match, the interrupt bit corresponding to this Receive Queue should be deasserted.

1Readback Mode. Indicates that the value that is presented on bits 31:2 of the read data should be read from this location and the interrupt for this Receive Queue should be asserted. This bit is read as zero.

4.45Function Address Register (FADDR)

The Function Address Register (FADDR) is shown in Figure 60 and described in Table 61.

		Figure 60. Function Address Register (FADDR)
7	6	0
Reserved		FUNCADDR
R-0		R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 61. Function Address Register (FADDR) Field Descriptions

Bit	Field	Value	Description
7	Reserved	0	Reserved
6-0	FUNCADDR	0-7Fh	7-bit address of the peripheral part of the transaction
			When used in Peripheral mode (DevCtl.D2=0), this register should be written with the address
			received through a SET_ADDRESS command, which will then be used for decoding the function
			address in subsequent token packets.

When used in Host mode (DevCtl.D2=1), this register should be set to the value sent in a

SET_ADDRESS command during device enumeration as the address for the peripheral device.

4.46 Power Management Register (POWER)

The Power Management Register (POWER) is shown in Figure 61 and described in Table 62.

Figure 61. Power Management Register (POWER)

7	6	5	4	3	2	1	0
ISOUPDATE	SOFTCONN	HSEN	HSMODE	RESET	RESUME	SUSPENDM	ENSUSPM
R/W-0	R/W-0	R/W-1	R-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 62. Power Management Register (POWER) Field Descriptions

Bit	Field	Value	Description
7	ISOUPDATE	0-1	When set, the USB controller will wait for an SOF token from the time TxPktRdy is set before
			sending the packet. If an IN token is received before an SOF token, then a zero length data packet
			will be sent. Note: This is only valid in Peripheral Mode. This bit only affects endpoints performing
			Isochronous transfers.
6	SOFTCONN	0-1	If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines are enabled when this bit
			is set and tri-stated when this bit is cleared. Note: This is only valid in Peripheral Mode.
5	HSEN	0-1	When set, the USB controller will negotiate for high-speed mode when the device is reset by the
			hub. If not set, the device will only operate in full-speed mode.
4	HSMODE	0-1	This bit is set when the USB controller has successfully negotiated for high-speed mode.
SPRUGH3–November 2008			Universal Serial Bus (USB) Controller	111
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