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Texas Instruments TMS320DM357 manual USB Interrupt Mask Set Register Intmsksetr

Models: TMS320DM357

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Registers

4.9USB Interrupt Mask Set Register (INTMSKSETR)

The USB Interrupt Mask Set Register (INTMSKSETR) is shown in Figure 24 and described in Table 25.

Figure 24. USB Interrupt Mask Set Register (INTMSKSETR)

31			25	24			16
		Reserved				USB
		R-0				W-0
15	13	12	8	7	5	4	0
	Reserved		RX	Reserved			TX
	R-0		W-0	R-0			W-0

LEGEND: R = Read only; W = Write only; -n= value after reset

Table 25. USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions

Bit	Field	Value	Description
31-25	Reserved	0	Reserved
24-16	USB	0-1FFh	Write a 1 to set equivalent USB interrupt mask
			Allows the USB interrupt masks to be individually enabled
15-13	Reserved	0	Reserved
12-8	RX	0-1Fh	Write a 1 to set equivalent Receive endpoint interrupt mask
			Allows the USB interrupt masks to be individually enabled
7-5	Reserved	0	Reserved
4-0	TX	0-Fh	Write a 1 to set equivalent Transmit endpoint interrupt mask
			Allows the USB interrupt masks to be individually enabled

SPRUGH3–November 2008	Universal Serial Bus (USB) Controller	89
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Texas Instruments TMS320DM357 manual USB Interrupt Mask Set Register Intmsksetr

Contents

Users Guide Submit Documentation Feedback Contents 100 Appendix a Type Register Host mode only HOSTTYPE0List of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Related Documentation From Texas Instruments Read This FirstNotational Conventions Notational Conventions Purpose of the Peripheral FeaturesFeatures Not Supported Cppi Functional Block DiagramExample 1. Initializing the USB Controller Supported Use Case ExamplesExample 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement USB Pins Signal DescriptionsClock Control Indexed and Non-Indexed RegistersDynamic Fifo Sizing USB PHY InitializationInterrupt Service Routine Flow Chart Peripheral Mode Control Transactions USB Controller Peripheral Mode OperationWrite Requests Zero Data RequestsRead Requests Endpoint 0 States CPU Actions at Transfer PhasesOUT Sequence of TransferEndpoint 0 Service Routine = Idle Service Endpoint 0 Flow ChartIdle Mode Flow Chart Idle ModeTX Mode Flow Chart TX ModeRX Mode Flow Chart RX ModeAdditional Conditions Error HandlingSetup Peripheral Mode Bulk In TransactionsBit Position Bit Field Name Configuration Bulk TransactionsOperation Peripheral Mode Bulk OUT TransactionsDisnyet Interrupt Transactions Isochronous in Transactions Isochronous TransactionsIsochronous OUT Transactions Set to 1 to enable isochronous protocol Host Mode Control Transactions USB Controller Host Mode OperationSetup Phase of a Control Transaction Flow Chart Setup PhaseRxpktrdy Data PhaseOUT Data Phase Data Phase Flow ChartOUT Data Phase Flow Chart Completion of Setup or OUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data PhaseOUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions DMA Transmit Operation DMA OperationTransmit Buffer Cppi Transmit Buffer DescriptorBits Name Description Transmit Buffer Descriptor WordBits Name Description 310 Buffer Pointer Descriptor. The software sets the Buffer PointerEOQ Transmit DMA StateOperation Transmit QueueTransparent Mode and Rndis Mode Transmit DMA Operation Transparent Mode Setup Rndis Mode SetupDMA Channel TearDown DMA Receive OperationReceive Buffer Descriptor Word Cppi Receive Buffer DescriptorBit Field Receive DMA StateReceive Queue Rx Queue Flow ChartUSB Controller Host and Peripheral Modes Operation Receive Abort Handling Rndis Mode and Transparent Mode Receive DMA OperationInterrupt Handling DMA Teardown ProcedureInterrupts Generated by the USB Controller USB Interrupt ConditionsUSB Interrupt Conditions DMA Interrupts Test ModesUSB Core Interrupts Testk TESTSE0NAKTestj Testpacket Forcehost Power Management Reset ConsiderationsInterrupt Support Edma Event SupportTransmit/Receive Cppi Channel 0 State Block Universal Serial Bus USB RegistersAcronym Register Description Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint Target Endpoint 4 Control Registers, Valid Only in Host Mode51Dh Bit Field Value Description Control Register CtrlrControl Register Ctrlr Field Descriptions Rndis Register Rndisr Status Register StatrStatus Register Statr Field Descriptions Rndis Register Rndisr Field DescriptionsAuto Request Register Autoreq Field Descriptions Auto Request Register AutoreqUSB USB Interrupt Source Register IntsrcrUSB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register IntsetrUSB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register IntclrrUSB Interrupt Mask Register Intmskr Field Descriptions USB Interrupt Mask Register IntmskrUSB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register IntmsksetrUSB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register IntmskclrrUSB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register IntmaskedrUSB Interrupt Vector Register Intvectr USB End of Interrupt Register EoirUSB End of Interrupt Register Eoir Field Descriptions USB Interrupt Vector Register Intvectr Field DescriptionsTransmit Cppi Teardown Register Tcppitdr Transmit Cppi Control Register TcppicrTransmit Cppi Control Register Tcppicr Field Descriptions Transmit Cppi Teardown Register Tcppitdr Field DescriptionsCppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register CppieoirTransmit Cppi Raw Status Register Tcppirawsr Transmit Cppi Masked Status Register TcppimsksrMasked Comppending ComppendingComppendingintren Transmit Cppi Interrupt Enable Set Register TcppiiensetrTransmit Cppi Interrupt Enable Clear Register Tcppiienclrr Receive Cppi Control Register Rcppicr RcppienableReceive Cppi Masked Status Register Rcppimsksr Receive Cppi Control Register Rcppicr Field DescriptionsReceive Cppi Raw Status Register Rcppirawsr Receive Cppi Interrupt Enable Set Register RcppiensetrReceive Buffer Count 0 Register RBUFCNT0 Receive Cppi Interrupt Enable Clear Register RcppiienclrrReceive Buffer Count 0 Register RBUFCNT0 Field Descriptions BufcntReceive Buffer Count 2 Register RBUFCNT2 Receive Buffer Count 1 Register RBUFCNT1Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Receive Buffer Count 2 Register RBUFCNT2 Field DescriptionsTransmit Cppi DMA State Word 0 TCPPIDMASTATEW0 Receive Buffer Count 3 Register RBUFCNT3Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions TxqheadptrTransmit Cppi DMA State Word 2 TCPPIDMASTATEW2 Transmit Cppi DMA State Word 1 TCPPIDMASTATEW1Sopdescriptorptr Currdescriptorptr TruncatednoneopTransmit Cppi DMA State Word 4 TCPPIDMASTATEW4 Transmit Cppi DMA State Word 3 TCPPIDMASTATEW3Transmit Cppi Completion Pointer Tcppicompptr Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5Sopbufferoffset Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 Rxqheadptr Receive Cppi DMA State Word 1 RCPPIDMASTATEW1Receive Cppi DMA State Word 3 RCPPIDMASTATEW3 Receive Cppi DMA State Word 2 RCPPIDMASTATEW2108 Pktlength Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Receive Cppi Completion Pointer Rcppicompptr Receive Cppi DMA State Word 6 RCPPIDMASTATEW6Sopbufferbytecnt CurrbufferbytecntPower Management Register Power Field Descriptions Power Management Register PowerReadback / Compare Mode Function Address Register FaddrField Descriptions Interrupt Register for Receive Endpoints 1 to 4 IntrrxEP4TX EP3TX EP2TX EP1TX EP0 EP4TXInterrupt Enable Register for Intrrx Intrrxe Interrupt Enable Register for Intrtx IntrtxeEP4RX EP3RX EP2RX EP1RX EP4RXInterrupt Enable Register for Intrrx Intrrxe Vbuserr Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendInterrupt Register for Common USB Interrupts Intrusb Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb IntrusbeFrame Number Register Frame Field Descriptions Frame Number Register FrameFramenumber EpselForcehost Register to Enable the USB 2.0 Test Modes TestmodeForcefs ForcehsMaxpayload Setupend ServsetupendFlushfifo ServrxpktrdyDatatog DatatogwrenClrdatatog ISO Mode Dmaen Frcdatatog DmamodeControl Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Dmaen Disnyet Dmamode Datatogwren DataerrnaktimeoutControl Status Register for Host Receive Endpoint Hostrxcsr 127 Receive Count Register Rxcount Count 0 Register COUNT0Count 0 Register COUNT0 Field Descriptions Receive Count Register Rxcount Field DescriptionsTransmit Type Register Host mode only Hosttxtype Type Register Host mode only HOSTTYPE0Type Register Host mode only HOSTTYPE0 Field Descriptions SpeedTransmit Interval Register Host mode only Hosttxinterval NAKLimit0 Register Host mode only HOSTNAKLIMIT0EP0NAKLIMIT PolintvlnaklimitSpeed Prot Rendpn Receive Type Register Host mode only HostrxtypeReceive Interval Register Host mode only Hostrxinterval Mprxe Configuration Data Register ConfigdataConfiguration Data Register Configdata Field Descriptions 133 Data Transmit and Receive Fifo Register for Endpoint 0 FIFO0Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 1 FIFO1Transmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 4 FIFO4 Transmit and Receive Fifo Register for Endpoint 3 FIFO3OTG Device Control Register Devctl Field Descriptions OTG Device Control Register DevctlBdevice Fsdev Lsdev Vbus Hostmode Hostreq Session BdeviceReceive Endpoint Fifo Size Rxfifosz Transmit Endpoint Fifo Size TxfifoszTransmit Endpoint Fifo Size Txfifosz Field Descriptions Receive Endpoint Fifo Size Rxfifosz Field DescriptionsReceive Endpoint Fifo Address Rxfifoaddr Transmit Endpoint Fifo Address TxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Field Descriptions AddrTransmit Hub Port Txhubport Transmit Function Address TxfuncaddrTransmit Hub Address Txhubaddr Receive Hub Port Rxhubport Receive Function Address RxfuncaddrReceive Hub Address Rxhubaddr 142 Additions/Modifications/Deletions Table A-1. Document Revision HistoryRfid Products ApplicationsDSP