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Table 62. Power Management Register (POWER) Field Descriptions (continued)
Bit | Field | Value | Description |
3 | RESET | This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write in Host | |
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| Mode, but |
2 | RESUME | Set to generate Resume signaling when the controller is in Suspend mode. The bit should be | |
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| cleared after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, this bit is also |
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| automatically set when Resume signaling from the target is detected while the USB controller is |
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| suspended. |
1 | SUSPENDM | In Host mode, this bit should be set to enter Suspend mode. In Peripheral mode, this bit is set on | |
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| entry into Suspend mode. It is cleared when the interrupt register is read, or the RESUME bit is set. |
0 | ENSUSPM | Set to enable the SUSPENDM output. |
4.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)
The Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) is shown in Figure 62 and described in Table 63.
Figure 62. Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)
| 15 |
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| 8 |
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| Reserved |
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| 7 |
| 5 | 4 | 3 | 2 | 1 | 0 |
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| Reserved |
| EP4TX | EP3TX | EP2TX | EP1TX | EP0 |
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LEGEND: R = Read only; |
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| Table 63. Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) | |||||||
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| Field Descriptions |
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Bit | Field | Value | Description |
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Reserved | 0 | Reserved |
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4 | EP4TX | Transmit Endpoint 4 interrupt active |
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3 | EP3TX | Transmit Endpoint 3 interrupt active |
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2 | EP2TX | Transmit Endpoint 2 interrupt active |
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1 | EP1TX | Transmit Endpoint 1 interrupt active |
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0 | EP0 | Endpoint 0 interrupt active |
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4.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
The Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) is shown in Figure 63 and described in Table 64.
112 | Universal Serial Bus (USB) Controller |
