USB Controller Host and Peripheral Modes Operation | www.ti.com |
3.2.2Bulk Transactions
3.2.2.1Host Mode: Bulk IN Transactions
A Bulk IN transaction may be used to transfer
The following optional features are available for use with an Rx endpoint used in host mode to receive the data:
∙Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception from the host. This allows that one packet can be received while another is being read. Double packet buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
∙DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception. Endpoint interrupt will be generated only in the error conditions.
∙AutoRequest: When the AutoRequest feature is enabled, the REQPKT bit of HOST_RXCSR (bit 5) will be automatically set when the RXPKTRDY bit is cleared.
This feature is applicable only when DMA is enabled. To enable AutoRequest feature, set the AUTOREQ register for the DMA channel associated for the endpoint.
3.2.2.1.1Setup
Before initiating any Bulk IN Transactions in Host mode:
∙The target function address needs to be set in the RXFUNCADDR register for the selected controller endpoint. (RXFUNCADDR register is available for all endpoints from EP0 to EP4.)
∙The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–Operating speed in the SPEED bit field (bits 7 and 6).
–Set 10 (binary value) in the PROT field for bulk transfer.
–Endpoint Number of the target device in RENDPN field. This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration.
∙The RXMAXP register for the controller endpoint must be written with the maximum packet size (in bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint.
∙The HOST_RXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215 frames/microframes), or cleared to 0 if the NAK timeout feature is not required.
∙The relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for this endpoint).
∙The following bits of HOST_RXCSR register should be set as shown below:
–Set DMAEN (bit 13) to 1 if a DMA request is required for this endpoint.
–Clear DSINYET (bit 12) to 0 to allow normal PING flow control. This will affect only High Speed transactions.
–Always clear DMAMODE (bit 11) to 0.
∙If DMA is enabled, the AUTOREQ register can be set for generating IN tokens automatically after receiving the data. Set the bit field RXn_AUTOREQ (where n is the endpoint number) with binary value 01 or 11.
When the endpoint is first configured, the endpoint data toggle should be cleared to 0 either by using the DATATOGWREN and DATATOG bits of HOST_RXCSR (bit 10 and bit 9) to toggle the current setting or by setting the CLRDATATOG bit of HOST_RXCSR (bit 7). This will ensure that the data toggle (which is handled automatically by the controller) starts in the correct state. Also if there are any data packets in the FIFO (indicated by the RXPKTRDY bit (bit 0 of HOST_RXCSR) being set), they should be flushed by setting the FLUSHFIFO bit of HOST_RXCSR (bit 4).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
52 | Universal Serial Bus (USB) Controller |
