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clear the Ownership bit in the DMA packet’s SOP buffer descriptor and issue an interrupt to the processor by writing the DMA packet’s last buffer descriptor address to the queue’s Tx DMA State Completion Pointer (TCPPICOMPPTR register). When the last packet in a queue has been transmitted, the DMA controller sets the End Of Queue bit in the EOP buffer descriptor, clears the Ownership bit in the SOP Descriptor, zeroes the appropriate DMA state head descriptor pointer, and then issues a Tx interrupt to the host by writing address of the last buffer descriptor processed by the DMA controller to the queue’s associated Tx completion pointer (TCPPICOMPPTR register).
On interrupt from the port, the software can process the buffer queue, detecting transmitted packets by the status of the Ownership bit in the SOP buffer descriptor. If the Ownership bit is cleared to zero, then the packet has been transmitted and the software may reclaim the buffers associated with the packet. The software continues queue processing until the end of the queue or until a SOP buffer descriptor is read that contains a set Ownership bit indicating that the packet transmission is not complete. The software determines that all packets in the queue have been transmitted when the last packet in the queue has a cleared Ownership bit in the SOP buffer descriptor, the End of Queue bit is set in the last packet EOP buffer descriptor, and the Next Descriptor Pointer of the last packet EOP buffer descriptor is zero.
The software acknowledges an interrupt by writing the address of the last buffer descriptor to the queue’s associated Tx Completion Pointer (TCPPICOMPPTR register).
If the software written buffer address value in TCCPICOMPPTR register is different from the buffer address written by the DMA controller after Tx completion, then the interrupt for the Tx Channel remains asserted. If the
A misqueued packet condition may occur when the software adds a packet to a queue for transmission as the DMA controller finishes transmitting the previous last packet in the queue. The misqueued packet is detected by the software when queue processing detects a cleared Ownership bit in the SOP buffer descriptor, a set End of Queue bit in the EOP buffer descriptor, and a nonzero Next Descriptor Pointer in the EOP buffer descriptor. A misqueued packet means that the DMA controller read the last EOP buffer descriptor before the host added the new last packet to the queue, so the DMA controller determined queue empty just before the last packet was added. The host software corrects the misqueued packet condition by initiating a new packet transfer for the misqueued packet by writing the misqueued packet’s SOP buffer descriptor address to the head descriptor pointer in TCCPIDMASTATEW0 register.
3.3.1.6Transparent Mode and RNDIS Mode Transmit DMA Operation
Transparent Mode DMA operation is the default DMA mode (as described in previous section) where an interrupt is generated whenever a DMA packet is transmitted. In the transparent mode, DMA packet size cannot be greater than USB MaxPktSize and FIFO size for the endpoint. This means, for transmitting say ‘n’ USB packets, the DMA controller should be programmed with a queue of ‘n’ DMA packets. Transparent mode must be used whenever USB MaxPktSize for the endpoint is not a multiple of 64 bytes.
RNDIS mode DMA is used to transmit DMA packets which are larger than USB MaxPktSize. This is accomplished by breaking the larger packet into smaller packets, not larger than USB MaxPktSize. This implies that the data to be transmitted will be sent over USB in multiple packets of MaxPktSize and the Tx DMA interrupt for the channel is generated after the transmission of complete DMA packet. This mode of DMA is used for RNDIS type transfers over USB. The protocol defines the end of the complete transfer by sending a short USB packet (smaller than USB MaxPktSize as mentioned in USB specification 2.0). If the DMA packet size is an exact multiple of USB MaxPktSize, the DMA controller sends a zero byte packet at the end of complete transfer to signify the completion of the transfer.
RNDIS Mode DMA is supported only when USB MaxPktSize and the associated FIFO size is an integral multiple of 64 bytes.
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