USB Controller Host and Peripheral Modes Operation | www.ti.com |
The software enables packet reception on a given channel by writing the address of the first buffer descriptor in the queue (nonzero value) to the channel’s head descriptor pointer (RCCPIDMASTATEW1) in the channel’s Rx DMA state. When packet reception begins on a given channel, the DMA controller fills each Rx buffer with data in order starting with the first buffer and proceeding through the Rx queue. If the Buffer Offset in the Rx DMA State is nonzero, then the controller will begin writing data after the offset number of bytes in the SOP buffer. The DMA controller performs the following operations at the end of each packet reception:
∙Overwrite the buffer length in the packet’s EOP buffer descriptor with the number of bytes actually received in the packet’s last buffer. The software initialized value is the buffer size. The overwritten value will be less than or equal to the software initialized value.
∙Set the EOP bit in the packet’s EOP buffer descriptor.
∙Set the EOQ bit in the packet’s EOP buffer descriptor if the current packet is the last packet in the queue.
∙Overwrite the packet’s SOP buffer descriptor Buffer Offset with the Rx DMA state value (the software initialized the buffer descriptor Buffer Offset value to zero). All non SOP buffer descriptors must have a zero Buffer Offset initialized by the host.
∙Overwrite the packet’s SOP buffer descriptor buffer length with the number of valid data bytes in the buffer. If the buffer is filled up, the buffer length will be the buffer size minus buffer offset.
∙Set the SOP bit in the packet’s SOP buffer descriptor.
∙Write the SOP buffer descriptor Packet Length field.
∙Clear the Ownership bit in the packet’s SOP buffer descriptor.
∙Issue an Rx DMA interrupt to the host processor by writing the address of the packet’s last buffer descriptor to the queue’s Rx DMA State Completion Pointer (RCPPICOMPPTR register).
On interrupt the software processes the Rx buffer queue detecting received packets by the status of the Ownership bit in each packet’s SOP buffer descriptor. If the Ownership bit is cleared then the packet has been completely received and is available to be processed by the software. The software may continue Rx queue processing until the end of the queue or until a buffer descriptor is read that contains a set Ownership bit indicating that the next packet’s reception is not complete. The software determines that the Rx queue is empty when the last packet in the queue has a cleared Ownership bit in the SOP buffer descriptor, a set End of Queue bit in the EOP buffer descriptor, and the Next Descriptor Pointer in the EOP buffer descriptor is zero.
The software acknowledges an interrupt by writing the address of the last buffer descriptor to the queue’s associated Rx Completion Pointer (RCPPICOMPPTR register).
If the software written buffer address value in RCCPICOMPPTR register is different from the buffer address written by the DMA controller after Rx completion, then the interrupt for the Rx Channel remains asserted. If the software written buffer address value matches with the buffer address written by the DMA controller, the Rx Channel interrupt gets deasserted.
A misqueued buffer may occur when the software adds buffers to a queue as the DMA controller finishes the reception of the previous last packet in the queue. The misqueued buffer is detected by the software when queue processing detects a cleared Ownership bit in the SOP buffer descriptor, a set End of Queue bit in the EOP buffer descriptor, and a nonzero Next Descriptor Pointer in the EOP buffer descriptor. A misqueued buffer means that the DMA controller read the last EOP buffer descriptor before the software added buffer descriptor(s) to the queue, so the DMA controller determined queue empty just before the software added more buffer descriptor(s). Receive overrun condition may occur in the misqueued buffer case. If a new packet reception is begun during the time that the DMA controller has determined the end of queue condition, then the received packet will overrun (start of packet overrun). If the misqueued buffer occurs during the middle of a packet reception then middle of packet overrun may occur. If the misqueued buffer occurs after the last packet has completed, and is corrected before the next packet reception begins, then overrun will not occur. The software acts on the misqueued buffer condition by writing the added buffer descriptor address to the appropriate Rx DMA State Head Descriptor Pointer in RCPPIDMASTATEW1 register.
66 | Universal Serial Bus (USB) Controller |
