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3.5.6FORCE_HOST
The Force Host test mode enables the user to instruct the core to operate in Host mode, regardless of whether it is actually connected to any peripheral, i.e., the state of the CID input and the LINESTATE and HOSTDISCON signals are ignored. (While in this mode, the state of the HOSTDISCON signal can be read from bit 7 of the DevCtl register.)
This mode, which is selected by setting bit 7 within the Testmode register, allows implementation of the USB Test_Force_Enable (7.1.20). It can also be used for debugging PHY problems in hardware.
While the Force_Host bit remains set, the core will enter Host mode when the Session bit is set and remain in Host mode until the Session bit is cleared even if a connected device is disconnected during the session. The operating speed while in this mode is determined for the sitting of the Force_HS and Force_FS bits of the Testmode register.
Universal Serial Bus (USB) Controller | 73 |