![](/images/new-backgrounds/1171214/171214191x1.webp)
Registers | www.ti.com |
4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
The Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) is shown in Figure 34 and described in Table 35.
Figure 34. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
31 |
|
|
|
| 16 |
|
|
| Reserved |
|
|
|
|
|
|
| |
15 |
|
| 4 | 3 | 0 |
|
| Reserved | COMP_PENDING_INTR_EN | ||
|
|
|
| ||
LEGEND: R/W = Read/Write; R = Read only; |
|
| |||
| Table 35. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions |
| |||
Bit | Field | Value | Description |
|
|
Reserved | 0 | Reserved |
|
| |
COMP_PENDING_INTR_EN | Transmit CPPI High Priority Interrupt Enables |
|
| ||
|
|
| These are active high interrupt enables corresponding to the Transmit CPPI High |
| |
|
|
| Priority Completion Pending status bits. |
|
|
4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
The Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) is shown in Figure 35 and described in Table 36.
Figure 35. Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
31 |
|
|
|
| 16 |
|
|
| Reserved |
|
|
|
|
|
|
| |
15 |
|
| 4 | 3 | 0 |
|
| Reserved | COMP_PENDING_INTR_EN | ||
|
|
|
| ||
LEGEND: R/W = Read/Write; R = Read only; |
|
| |||
| Table 36. Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions | ||||
Bit | Field | Value | Description |
|
|
Reserved | 0 | Reserved |
|
| |
COMP_PENDING_INTR_EN | Writing a 1 to any of the bits in the Transmit CPPI Interrupt Enable Clear Register will | ||||
|
|
| result in clearing of the corresponding bit in the Transmit CPPI High Priority Interrupt | ||
|
|
| Enable Register. |
|
|
96 | Universal Serial Bus (USB) Controller |