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3.1.4Isochronous Transactions
3.1.4.1Isochronous IN Transactions
An Isochronous IN transaction is used to transfer periodic data from the function controller to the host.
The following optional features are available for use with a Tx endpoint used in Peripheral mode for Isochronous IN transactions:
∙Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting transmission to the host. Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ register (bit 4).
Note: Double packet buffering is generally advisable for Isochronous transactions in order to avoid Underrun errors as described in later section.
∙DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO. This feature allows the DMA controller to load packets into the FIFO without processor intervention.
However, this feature is not particularly useful with Isochronous endpoints because the packets transferred are often not maximum packet size and the PERI_TXCSR register needs to be accessed following every packet to check for Underrun errors.
When DMA is enabled and DMAMODE bit of PERI_TXCSR is set, endpoint interrupt will not be generated for completion of packet transfer. Endpoint interrupt will be generated only in the error conditions.
3.1.4.1.1Setup
In configuring a Tx endpoint for Isochronous IN transactions, the TXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for this endpoint) and the PERI_TXCSR register should be set as shown in Table 4.
Table 4. PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions
Bit Position | Bit Field Name | Configuration |
Bit 14 | ISO | Set to 1 to enable Isochronous transfer protocol |
Bit 13 | MODE | Set to 1 to ensure the FIFO is enabled (only necessary if the FIFO is shared with an Rx |
|
| endpoint). |
Bit 12 | DMAEN | Set to 1 if DMA Requests have to be enabled |
Bit 11 | FRCDATATOG | Ignored in Isochronous mode |
Bit 10 | DMAMODE | Set it to 1, when DMA is enabled and EP interrupt is not needed for each packet transmission |
3.1.4.1.2Operation
An Isochronous endpoint does not support data retries, so if data underrun is to be avoided, the data to be sent to the host must be loaded into the FIFO before the IN token is received. The host will send one IN token per frame (or microframe in
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